/*
 * $Id:   Broadcom SDK $
 * $Copyright: Copyright 2011 Broadcom Corporation.
 * This program is the proprietary software of Broadcom Corporation
 * and/or its licensors, and may only be used, duplicated, modified
 * or distributed pursuant to the terms and conditions of a separate,
 * written license agreement executed between you and Broadcom
 * (an "Authorized License").  Except as set forth in an Authorized
 * License, Broadcom grants no license (express or implied), right
 * to use, or waiver of any kind with respect to the Software, and
 * Broadcom expressly reserves all rights in and to the Software
 * and all intellectual property rights therein.  IF YOU HAVE
 * NO AUTHORIZED LICENSE, THEN YOU HAVE NO RIGHT TO USE THIS SOFTWARE
 * IN ANY WAY, AND SHOULD IMMEDIATELY NOTIFY BROADCOM AND DISCONTINUE
 * ALL USE OF THE SOFTWARE.  
 *  
 * Except as expressly set forth in the Authorized License,
 *  
 * 1.     This program, including its structure, sequence and organization,
 * constitutes the valuable trade secrets of Broadcom, and you shall use
 * all reasonable efforts to protect the confidentiality thereof,
 * and to use this information only in connection with your use of
 * Broadcom integrated circuit products.
 *  
 * 2.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS
 * PROVIDED "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
 * REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY,
 * OR OTHERWISE, WITH RESPECT TO THE SOFTWARE.  BROADCOM SPECIFICALLY
 * DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
 * NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
 * ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
 * CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
 * OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
 * 
 * 3.     TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
 * BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL,
 * INCIDENTAL, SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER
 * ARISING OUT OF OR IN ANY WAY RELATING TO YOUR USE OF OR INABILITY
 * TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF
 * THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF OR USD 1.00,
 * WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY NOTWITHSTANDING
 * ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.$
 * 
 * SOC Property Names (Autogenerated)
 * 
 * DO NOT EDIT THIS FILE. Your changes will be lost
 */
#ifndef _SOC_PROPERTY_H
#define _SOC_PROPERTY_H


/*
 * Station mac address used for management through the switch ports
 * itself. If using the CPU network interface, the NVRAM setting is used
 * for MAC address assignment.
 */
#define spn_STATION_MAC_ADDRESS  "station_mac_address"
/*
 * Enable polled IRQ mode (useful for board bringup and debugging).
 * IRQs will be polled from a dedicated thread and hardware interrupts
 * will remain disabled.
 */
#define spn_POLLED_IRQ_MODE  "polled_irq_mode"
/*
 * The priority of the IRQ poll thread as well as the minimum delay
 * between IRQ polls can be configured if needed.
 */
#define spn_POLLED_IRQ_DELAY  "polled_irq_delay"
/*
 * The priority of the IRQ poll thread as well as the minimum delay
 * between IRQ polls can be configured if needed.
 */
#define spn_POLLED_IRQ_PRIORITY  "polled_irq_priority"
/*
 * Allow filtering to be disabled in hardware if not being used.
 * Also, tables will not be cleared which can save time in simulation.
 */
#define spn_FILTER_ENABLE  "filter_enable"

/* Initial number of COS queues bcm_init() configures the chip for. */
#define spn_BCM_NUM_COS  "bcm_num_cos"

/* Clear the filter table for 10/100Mb ports during initialization */
#define spn_BCM_FILTER_CLEAR_FE  "bcm_filter_clear_fe"

/* Clear the filter table for 1000Mb ports during initialization */
#define spn_BCM_FILTER_CLEAR_GE  "bcm_filter_clear_ge"

/* Clear the filter table for 10GE ports during initialization */
#define spn_BCM_FILTER_CLEAR_XE  "bcm_filter_clear_xe"
/*
 * Linkscan:
 * Specify ports on which bcm_init will run linkscan (default all).
 */
#define spn_BCM_LINKSCAN_PBMP  "bcm_linkscan_pbmp"
/*
 * Linkscan interval in microseconds.
 * If non-zero, bcm_init() will start linkscan
 */
#define spn_BCM_LINKSCAN_INTERVAL  "bcm_linkscan_interval"
/*
 * The number of port update errors which will cause the bcm_linkscan module
 * to suspend a port from update processing for the period of time set in
 * "bcm_linkscan_errdelay".
 */
#define spn_BCM_LINKSCAN_MAXERR  "bcm_linkscan_maxerr"
/*
 * The amount of time in microseconds for which the bcm_linkscan module
 * will suspend a port from further update processing after
 * "bcm_linkscan_maxerr" errors are detected.  After this delay, the
 * error state for the port is cleared and normal linkscan processing
 *  resumes on the port.
 */
#define spn_BCM_LINKSCAN_ERRDELAY  "bcm_linkscan_errdelay"
/*
 * BCM Statistics Collection:
 * Set bitmap of ports on which stat collection will be enabled.
 * Default is all ports.
 */
#define spn_BCM_STAT_PBMP  "bcm_stat_pbmp"
/*
 * Set stat collection interval in microseconds.
 * Setting this to 0 will prevent counters from being started.
 */
#define spn_BCM_STAT_INTERVAL  "bcm_stat_interval"

/* Timeout delay in microseconds before bcm_stat_sync returns BCM_E_TIMEOUT */
#define spn_BCM_STAT_SYNC_TIMEOUT  "bcm_stat_sync_timeout"
/*
 * Flag values to be ORd together:
 *    0x0 indicates that counter DMA should NOT be used
 *    0x1 indicates that counter DMA should be used (default).
 */
#define spn_BCM_STAT_FLAGS  "bcm_stat_flags"
/*
 * Threshold value for oversize (*OVR) frame size.
 * Values over 1518 affect the *OVR statistics computation
 */
#define spn_BCM_STAT_JUMBO  "bcm_stat_jumbo"

/* Specifies the priority of the BCM TX thread */
#define spn_BCM_TX_THREAD_PRI  "bcm_tx_thread_pri"

/* Specifies the priority of the BCM RX thread */
#define spn_BCM_RX_THREAD_PRI  "bcm_rx_thread_pri"

/* Specifies the priority of the BCM Linkscan thread */
#define spn_LINKSCAN_THREAD_PRI  "linkscan_thread_pri"

/* Specifies the priority of the BCM Portmon thread */
#define spn_PORTMON_THREAD_PRI  "portmon_thread_pri"

/* Packet DMA abort timeout */
#define spn_PDMA_TIMEOUT_USEC  "pdma_timeout_usec"

/* Counter DMA collection pass timeout in microseconds */
#define spn_CDMA_TIMEOUT_USEC  "cdma_timeout_usec"
/*
 * Manually collect the HOLD register in the counter DMA thread on
 * BCM568xx and BCM567xx devices.
 */
#define spn_CDMA_PIO_HOLD_ENABLE  "cdma_pio_hold_enable"

/* Table DMA operation timeout in microseconds */
#define spn_TDMA_TIMEOUT_USEC  "tdma_timeout_usec"

/* Table DMA operation should use interrupt rather than poll for completion */
#define spn_TDMA_INTR_ENABLE  "tdma_intr_enable"

/* Table SLAM DMA operation timeout in microseconds */
#define spn_TSLAM_TIMEOUT_USEC  "tslam_timeout_usec"

/* Table SLAM DMA operation should use interrupt rather than poll for completion */
#define spn_TSLAM_INTR_ENABLE  "tslam_intr_enable"

/* CCM DMA operation timeout in microseconds */
#define spn_CCMDMA_TIMEOUT_USEC  "ccmdma_timeout_usec"

/* CCM DMA operation should use interrupt rather than poll for completion */
#define spn_CCMDMA_INTR_ENABLE  "ccmdma_intr_enable"
/*
 * Maximum number of consecutive S-channel errors the counter collection
 * code will tolerate before the counter thread gives up and exits.
 */
#define spn_SOC_CTR_MAXERR  "soc_ctr_maxerr"
/*
 * Skip hardware reset (CMIC_CONFIG.RESET_CPS) when calling soc_reset().
 * This means that e.g. 'init soc' will NOT perform a hard reset.
 */
#define spn_SOC_SKIP_RESET  "soc_skip_reset"

/* Miscellaneous thread priorities; 0 is highest and 255 is lowest */
#define spn_COUNTER_THREAD_PRI  "counter_thread_pri"

/* Check callback return code and abort on error. */
#define spn_CB_ABORT_ON_ERR  "cb_abort_on_err"
/*
 * When a link goes down for any reason, the driver waits for all packets
 * to that port to drain from the MMU before continuing.  There is a
 * timeout in case the packet count is non-zero AND non-decrementing.
 */
#define spn_LCCDRAIN_TIMEOUT_USEC  "lccdrain_timeout_usec"
#define spn_SOC_SCOREBOARD_ENABLE  "soc_scoreboard_enable"
#define spn_SOC_SCOREBOARD_INTERVAL  "soc_scoreboard_interval"

/* L3 switching enable */
#define spn_L3_ENABLE  "l3_enable"

/* IMPC switching enable */
#define spn_IPMC_ENABLE  "ipmc_enable"

/* Include the VLAN as part of the hash key for L3 IPMC */
#define spn_IPMC_DO_VLAN  "ipmc_do_vlan"

/* Switch devices are connected via the HiGig port (fabric devices OK). */
#define spn_TRUNK_EXTEND  "trunk_extend"
/*
 * Delay this long after an ARL message overrun before a lengthy ARL-
 * resync process.  Setting to 0 to disables resync, in peril of getting
 * an inconsistent ARL message stream and/or corrupt L2 shadow table.
 */
#define spn_ARL_RESYNC_DELAY  "arl_resync_delay"

/* Enable L2X shadowing into AVL tree. */
#define spn_L2XMSG_AVL  "l2xmsg_avl"
/*
 * Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
 * L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
 */
#define spn_L2XMSG_MODE  "l2xmsg_mode"
/*
 * Priority of the _soc_l2x_thread, that used to synchronize
 * shadow copy of the L2 entry with the HW table
 */
#define spn_L2XMSG_THREAD_PRI  "l2xmsg_thread_pri"
/*
 * Period between synchronizations of the software L2X shadow table
 * with the hardware (5690 only).  The thread actually runs every
 * l2xmsg_thread_usec/l2xmsg_chunks microseconds.
 */
#define spn_L2XMSG_THREAD_USEC  "l2xmsg_thread_usec"
/*
 * The l2xmsg thread will call back to the user any time an L2X address
 * is added, removed, or changed.  However, if only the hit bit changes,
 * it will not call back unless l2xmsg_shadow_hit_bits is set to 1.
 */
#define spn_L2XMSG_SHADOW_HIT_BITS  "l2xmsg_shadow_hit_bits"
/*
 * The l2xmsg thread will call back to the user any time an L2X address
 * is added, removed, or changed.  However, if only the source hit bit changes,
 * it will not call back unless l2xmsg_shadow_hit_bits is set to 0 and
 * l2xmsg_shadow_hit_src is set to 1.
 */
#define spn_L2XMSG_SHADOW_HIT_SRC  "l2xmsg_shadow_hit_src"
/*
 * The l2xmsg thread will call back to the user any time an L2X address
 * is added, removed, or changed.  However, if only the destination hit bit changes,
 * it will not call back unless l2xmsg_shadow_hit_bits is set to 0 and
 * l2xmsg_shadow_hit_dst is set to 1.
 */
#define spn_L2XMSG_SHADOW_HIT_DST  "l2xmsg_shadow_hit_dst"
/*
 * Synchronize the L2X table in chunks to spread out the work over
 * time and save memory on size of DMA buffer.  Must be power of 2.
 */
#define spn_L2XMSG_CHUNKS  "l2xmsg_chunks"

/* Size of the buffer that is used to drain L2 FIFO when working in the L2 FIFO mode */
#define spn_L2XMSG_HOSTBUF_SIZE  "l2xmsg_hostbuf_size"
/*
 * Timeout for hardware-accelerated ARL delete operations including:
 * delete by port, delete by port+modid, delete by VLAN, delete by trunk.
 */
#define spn_ARL_CLEAN_TIMEOUT_USEC  "arl_clean_timeout_usec"

/* Specifies the priority of the memory scanning and error correction thread */
#define spn_MEM_SCAN_THREAD_PRI  "mem_scan_thread_pri"
/*
 * Specifies the number of table entries to be retrieved at a time
 * during memory scanning.
 */
#define spn_MEM_SCAN_CHUNK_SIZE  "mem_scan_chunk_size"
/*
 * S-Channel operation timeout in microseconds.  Note that ARL
 * insert/delete messages can take a while if the ARL is highly active.
 */
#define spn_SCHAN_TIMEOUT_USEC  "schan_timeout_usec"

/* MIIM operation timeout in microseconds */
#define spn_MIIM_TIMEOUT_USEC  "miim_timeout_usec"

/* Memory Built-In-Self-Test (BIST) timeout in milliseconds */
#define spn_BIST_TIMEOUT_MSEC  "bist_timeout_msec"
/*
 * Normally, the system will use polling for register/memory S-Channel
 * operations and interrupts for time-consuming operations such as ARL
 * insert/delete.  If this schan_intr_enable is set to 0, polling will be
 * used for ALL operations.
 */
#define spn_SCHAN_INTR_ENABLE  "schan_intr_enable"
/*
 * Length of time to block the S-Channel error interrupt after one occurs.
 * Prevents monopolizing the CPU (use 0 to disable any blocking).
 */
#define spn_SCHAN_ERROR_BLOCK_USEC  "schan_error_block_usec"
/*
 * If miim_intr_enable variable is set to 1, the system will use
 * interrupts for MII operations since they take a while (70 usec or so).
 * If this variable is set to 0, polling will be used for all MII
 * operations.
 */
#define spn_MIIM_INTR_ENABLE  "miim_intr_enable"
/*
 * Limit the number of ARL messages/sec the software will process, to
 * keep it from hogging the CPU.  Set to 0 to disable.
 * Does not apply to L2X shadow table (see l2xmsg_thread_usec instead).
 */
#define spn_ARL_RATE_LIMIT  "arl_rate_limit"

/* MMU SDRAM configuration */
#define spn_MMU_SDRAM_ENABLE  "mmu_sdram_enable"
/*
 * Diagnostics loopback (tr 17 through tr 24) timeout in seconds for
 * loopback packet reception
 */
#define spn_DIAG_LB_PACKET_TIMEOUT  "diag_lb_packet_timeout"
/*
 * Diagnostics loopback - if set to TRUE, all receive buffers are filled
 * with 0xdeadbeef before DMAing into them.  It is slow, but then you will
 * know if loopback miscompares are due to skipped PCI writes.
 */
#define spn_DIAG_LB_FILL_RX  "diag_lb_fill_rx"

/* Packet watcher thread priority */
#define spn_DIAG_PW_THREAD_PRI  "diag_pw_thread_pri"
/*
 * When set to >= 68, packet watcher will run in truncating mode,
 * allocating smaller Rx buffers and accepting oversized packets on
 * all Rx DMA channels.
 */
#define spn_DIAG_PW_BUFFER_SIZE  "diag_pw_buffer_size"

/* Select memory tests run by cfapinit (default MT_PAT_FIVES and MT_PAT_AS) */
#define spn_CFAP_TESTS  "cfap_tests"
/*
 * If phy_enable is set to 0, all ports will use the null PHY driver.
 * This is useful for simulations on Quickturn.
 */
#define spn_PHY_ENABLE  "phy_enable"
/*
 * If phy_null_<port> is set to 1, the port will use the null PHY driver.
 * This is useful for configuring direct-connect GMII links such as the
 * chip-to-chip links on a 48-port board (example shown for 48 port board).
 */
#define spn_PHY_NULL  "phy_null"

/* If phy_simul_<port> is set to 1, the port will use the simulation. */
#define spn_PHY_SIMUL  "phy_simul"

/* Fiber vs. copper autodetection enable. */
#define spn_PHY_AUTOMEDIUM  "phy_automedium"
/*
 * Fiber vs. copper preference
 * When automedium is enabled, phy_fiber_pref indicates which medium to
 * prefer if BOTH are active.  Selects fiber (1) or copper (0).
 * When automedium is disabled, phy_fiber_pref indicates which medium to
 * use.  Selects fiber (1) or copper (0).
 */
#define spn_PHY_FIBER_PREF  "phy_fiber_pref"
/*
 *  Fiber de-glitch: some GBICs may cause a brief fiber energy detect
 *  when inserted, even without a link.  This could cause the copper link
 *  to be dropped, so an energy detect de-glitch is provided.  The
 *  phy_fiber_deglitch_usecs is the de-glitch time in usec. This is
 *  only applied to BCM5421S PHY device.
 */
#define spn_PHY_FIBER_DEGLITCH_USECS  "phy_fiber_deglitch_usecs"

/* Per-port parameter on maximum time to wait for PHY autoneg busy condition. */
#define spn_PHY_AUTONEG_TIMEOUT  "phy_autoneg_timeout"
#define spn_PHY_SERDES  "phy_serdes"
/*
 * Serdes Autonegotiation configuration
 * This per-port parameter specifies what will happen if autonegotiation is
 * on but the remote partner is not autonegotiating.  If the value is zero,
 * we will not link.  If the value is non-zero, we will link.
 */
#define spn_PHY_SERDES_AUTOS  "phy_serdes_autos"

/* This specifies the external PHY device is BCM5464S. */
#define spn_PHY_5464S  "phy_5464S"

/* This specifies the external PHY device is BCM5690. */
#define spn_PHY_5690  "phy_5690"

/* This specifies the external PHY device is BCM8706 and equivalent. */
#define spn_PHY_8706  "phy_8706"

/* This specifies the external PHY device is BCM8072 and equivalent. */
#define spn_PHY_8072  "phy_8072"

/* This specifies the external PHY device is BCM84740. */
#define spn_PHY_84740  "phy_84740"

/* This specifies the external PHY device is BCM84753. */
#define spn_PHY_84753  "phy_84753"

/* This specifies the external PHY device is BCM84754. */
#define spn_PHY_84754  "phy_84754"

/* This specifies the external PHY device is BCM84064. */
#define spn_PHY_84064  "phy_84064"

/* Specify the physical lane number corresponding to the logical lane0 . */
#define spn_PHY_LANE0_L2P_MAP  "phy_lane0_l2p_map"

/* This controls the clause 73 auto-negotiation, enable(1), disable(0). */
#define spn_PHY_AN_C73  "phy_an_c73"
/*
 * This controls whether to load the external ROM microcode to the
 *  applicable PHY devices, load(1), not load(0).
 */
#define spn_PHY_EXT_ROM_BOOT  "phy_ext_rom_boot"
/*
 * This indicates whether the long cable is used on the external PHY device
 *  with XFI interface, By default XFI cannot drive long distance cables.
 *  TX preemphasis needs to be adjusted if long cables are used on the XFI side.
 */
#define spn_PHY_LONG_XFI  "phy_long_xfi"

/* this controls half power mode for applicable PHY devices, enable(1), disable(0). */
#define spn_PHY_HALF_POWER  "phy_half_power"
/*
 * set BCM5488 family PHY to operate in class A/B low power mode.
 *  Accept value 0(lowest power) to 7(highest power).
 */
#define spn_PHY_LOW_POWER_MODE  "phy_low_power_mode"

/* indicate which port is the first port of the octal PHY. */
#define spn_PHY_OCTAL_PORT_FIRST  "phy_octal_port_first"
/*
 * Set the given XGXS control mode in independent channel mode for
 *  Hyperlite/Hypercore/Warpcore serdes. Valid value 4,5, and 6
 */
#define spn_PHY_HL65_1LANE_MODE  "phy_hl65_1lane_mode"
/*
 * phy53115_a0 sw-workaround for the link issue at AN+100TX mode.
 * 	0 - disable this SW workaround.
 * 	1 - enable this SW workaround.
 */
#define spn_PHY_53115_AN100TX_WAR  "phy_53115_an100tx_war"
/*
 * phy53115_b0 sw-workaround for the interoperability issue.
 * 	0 - disable this SW workaround.
 * 	1 - enable this SW workaround.
 * --- This SW-WAR also active for fixing bcm53118_a0 at IOP problem.
 */
#define spn_PHY_53115_B0_IOP_WAR  "phy_53115_b0_iop_war"
/*
 * Specify switch port on BCM8040. The switch port is the port
 *  connecting to MAC side device.
 */
#define spn_PHY_8040_SWITCH_PORT  "phy_8040_switch_port"

/* Specify mux port0 on BCM8040. A mux port will connect to another PHY device. */
#define spn_PHY_8040_MUX_PORT0  "phy_8040_mux_port0"

/* Specify mux port1 on BCM8040. A mux port will connect to another PHY device. */
#define spn_PHY_8040_MUX_PORT1  "phy_8040_mux_port1"
/*
 * Specify mux port2 on BCM8040. A mux port will connect to another PHY device.
 * The port is treated as invalid if there is no PHY device connecting to
 */
#define spn_PHY_8040_MUX_PORT2  "phy_8040_mux_port2"

/* Specify 53314 PHY device operating frequency as 156.25MHz. */
#define spn_PHY_53314_CLK156  "phy_53314_clk156"

/* Specify the external PHY device uses I2C bus instead of MDIO bus */
#define spn_PHY_BUS_I2C  "phy_bus_i2c"

/* Specify the external PHY device is a copper SFP PHY */
#define spn_PHY_COPPER_SFP  "phy_copper_sfp"

/* The PHY has a fiber medium in addition to a copper medium */
#define spn_PHY_FIBER_CAPABLE  "phy_fiber_capable"
/*
 * Bypass the PCS retimer function to provide better latency.
 * However it requires a more clean input clock than in retimer mode
 */
#define spn_PHY_PCS_REPEATER  "phy_pcs_repeater"

/* gig port i/o voltage control on BCM5615 and similar devices */
#define spn_GIG_IOV  "gig_iov"

/* Force the port into TBI(10-bit interface) mode */
#define spn_IF_TBI  "if_tbi"

/* Set 10G+ stack ports to default to B5632 encapsulation instead of Higig format */
#define spn_BCM5632_MODE  "bcm5632_mode"

/* Reset meters for 10/100Mb ports during initialization */
#define spn_BCM_METER_CLEAR_FE  "bcm_meter_clear_fe"

/* Reset meters for 1000Mb ports during initialization */
#define spn_BCM_METER_CLEAR_GE  "bcm_meter_clear_ge"

/* Reset meters for 10GE ports during initialization */
#define spn_BCM_METER_CLEAR_XE  "bcm_meter_clear_xe"
/*
 * Fusion/Uni core preemphasis, driver current and  pre-driver current
 * values 0-15 (can be changed per-port)
 */
#define spn_XGXS_PREEMPHASIS  "xgxs_preemphasis"

/* Configure the given driver current value for applicable XGXS serdes devices. */
#define spn_XGXS_DRIVER_CURRENT  "xgxs_driver_current"

/* Configure the given pre driver current value for applicable XGXS serdes devices. */
#define spn_XGXS_PRE_DRIVER_CURRENT  "xgxs_pre_driver_current"

/* Fusion PLL lock range value 0-15 (can be changed per-port) */
#define spn_XGXS_PLLLOCK  "xgxs_plllock"

/* Set the specific RX equalizer control value for applicable XGXS devices */
#define spn_XGXS_EQUALIZER  "xgxs_equalizer"
/*
 * Set the specific offset which is part of RX equalizer control value
 *  for applicable XGXS devices
 */
#define spn_XGXS_OFFSET  "xgxs_offset"

/* Use crystal input for LCPLL */
#define spn_XGXS_LCPLL_XTAL_REFCLK  "xgxs_lcpll_xtal_refclk"
/*
 * Fusion core reference clock selection
 *  External Clock = 0, Internal LCPLL = 1
 */
#define spn_XGXS_LCPLL  "xgxs_lcpll"

/* Fusion core LCPLL clock speed selection - 10Gbps = 0, 12Gbps = 1 */
#define spn_XGXS_LCPLL_12GBPS  "xgxs_lcpll_12gbps"

/* Unicore 10G parallel detect (10/12 Gbps legacy speed detection) */
#define spn_XGXS_PDETECT_10G  "xgxs_pdetect_10g"

/* Remap XGXS tx lanes to desired mapping. See xgxs_rx_lane_map */
#define spn_XGXS_TX_LANE_MAP  "xgxs_tx_lane_map"
/*
 * Remap XGXS rx lanes to desired mapping. Four bits were used for
 * specifying each lane in the format of Lane 0 (bit 15-12), Lane 1 (bit 11-8),
 * lane 2 (bit 7-4), and lane 3 (bit 3-0).
 * For example, to reverse the rx lane mapping in 3, 2, 1, 0 order,
 * set xgxs_rx_lane_map=0x3210.
 * However for Warpcore serdes device, the format is in reversed order, i.e. 
 * Lane 3 (bit 15-12), Lane 2 (bit 11-8),lane 1 (bit 7-4), and lane 0 (bit 3-0),
 * The example above will be: set xgxs_rx_lane_map=0x0123.
 */
#define spn_XGXS_RX_LANE_MAP  "xgxs_rx_lane_map"
/*
 * Serdes reference clock selection External Clock = 0,
 *  Internal LCPLL = 1
 */
#define spn_SERDES_LCPLL  "serdes_lcpll"

/* Serdes core preemphasis. values 0-15 (can be changed per-port) */
#define spn_SERDES_PREEMPHASIS  "serdes_preemphasis"

/* Serdes core pre-driver current. values 0-15 (can be changed per-port) */
#define spn_SERDES_PRE_DRIVER_CURRENT  "serdes_pre_driver_current"

/* Serdes core driver current. values 0-15 (can be changed per-port) */
#define spn_SERDES_DRIVER_CURRENT  "serdes_driver_current"
/*
 * Configure signal auto-detection between SGMII and fiber
 *  Note this only works when auto-negotiation is enabled.
 */
#define spn_SERDES_AUTOMEDIUM  "serdes_automedium"

/* This manually selects either fiber or SGMII when auto-detection is off */
#define spn_SERDES_FIBER_PREF  "serdes_fiber_pref"

/* switch serdes SGMII master/slave mode configuration.  Default is slave. */
#define spn_SERDES_SGMII_MASTER  "serdes_sgmii_master"

/* Enable/disable two lane XAUI interface on applicable serdes devices */
#define spn_SERDES_2WIRE_XAUI  "serdes_2wire_xaui"

/* Enable serdes Loss Of Signal(LOS) function. 0 disable, 1 enable */
#define spn_SERDES_RX_LOS  "serdes_rx_los"

/* Invert serdes LOS signal level. 0 not invert, 1 invert */
#define spn_SERDES_RX_LOS_INVERT  "serdes_rx_los_invert"
/*
 * Selects the primary L1 clock recovery port.
 * Choose a non-cpu port that does not have an external phy.
 */
#define spn_L1_PRIMARY_CLK_RECOVERY_PORT  "L1_primary_clk_recovery_port"
/*
 * Selects the backup L1 clock recovery port.
 * Choose a non-cpu port that does not have an external phy.
 */
#define spn_L1_BACKUP_CLK_RECOVERY_PORT  "L1_backup_clk_recovery_port"
/*
 * BCM5665L and BCM5666L support
 * The BCM5665L and BCM5666L device IDs are 0x5665, same as the BCM5665.
 * However, these devices do not support the upper 24 FE ports.
 * The following property must be used to invalidate them.
 */
#define spn_PBMP_VALID  "pbmp_valid"
/*
 * Configure the memory tests run during BCM5670 initialization
 * (using MT_PAT_* flags)
 */
#define spn_LLA_TESTS  "lla_tests"
#define spn_STACK_ENABLE  "stack_enable"
#define spn_STACK_SIMPLEX  "stack_simplex"

/* Stack master priority for stacking examples. */
#define spn_STACK_CPU_PRIORITY  "stack_cpu_priority"
/*
 * By default, 5670 will be configured to accept the maximum number of
 * packets per port, but may drop them if resources are oversubscribed due
 * to activity from other ports.  If lossless mode is enabled, 5670 will
 * instead be configured to accept packets only if sufficient processing
 * resources are guaranteed for all ports.  This may decrease overall
 * throughput, but no accepted packets will be dropped.
 */
#define spn_LOSSLESS_MODE  "lossless_mode"
/*
 * Allow a BCM5675 fabric device to mirror using the same method as
 * a BCM5670 fabric.
 */
#define spn_MIRROR_5670_MODE  "mirror_5670_mode"

/* Configure a BCM5675 fabric device to to operate with a 12G core clock. */
#define spn_CORE_CLOCK_12G  "core_clock_12G"
/*
 * BCM5675 HOL blocking avoidance mode (jitter and hysteresis)
 * Set this to 1 to enable jitter for comparing low cell/packet count thresholds
 */
#define spn_MMU_HOL_JITTER  "mmu_hol_jitter"

/* Set this to 1 to enable hysteresis with recommended default low thresholds */
#define spn_MMU_HOL_HYSTERESIS  "mmu_hol_hysteresis"

/* Specify IEEE MII reset timeout value for copper PHY devices */
#define spn_PHY_RESET_TIMEOUT  "phy_reset_timeout"
/*
 * 24c64 EEPROM and XFP share the same I2C slave address. Set this to
 * 1 to treat the device found at this slave address as XFP.
 */
#define spn_I2C_NVRAM_SKIP  "i2c_nvram_skip"
/*
 * PCF8574 lpt2 and LTC4258 poe3 share the same I2C slave address. Set
 * this to 1 to treat the device found at this slave address as POE.
 */
#define spn_I2C_HCLK_SKIP  "i2c_hclk_skip"
/*
 * PD63000 init power setting. Set this to 1 for 100W; otherwise
 * default of 37W is used.
 */
#define spn_I2C_POE_POWER  "i2c_poe_power"

/* Swap XGXS device tx lane 0, 1, 2, 3 to lane 3, 2, 1, 0 on 10G PHYs */
#define spn_PHY_XAUI_TX_LANE_SWAP  "phy_xaui_tx_lane_swap"

/* Swap XGXS device rx lane 0, 1, 2, 3 to lane 3, 2, 1, 0 on 10G PHYs */
#define spn_PHY_XAUI_RX_LANE_SWAP  "phy_xaui_rx_lane_swap"
/*
 * Flip XAUI lane TX polarity on applicable serdes devices
 * value of 1 - Flip TX polarity on all lane(s) of the port.
 * value of 0x000F - Flip TX polarity on lane 0.
 * value of 0x00F0 - Flip TX polarity on lane 1.
 * value of 0x0F00 - Flip TX polarity on lane 2.
 * value of 0xF000 - Flip TX polarity on lane 3.
 */
#define spn_PHY_XAUI_TX_POLARITY_FLIP  "phy_xaui_tx_polarity_flip"

/* Flip XAUI lane RX polarity. See phy_xaui_tx_polarity_flip for values */
#define spn_PHY_XAUI_RX_POLARITY_FLIP  "phy_xaui_rx_polarity_flip"
/*
 * Flip PHY lane TX polarity on applicable PHY devices
 * value of 1 - Flip TX polarity on all lane(s) of the port.
 * value of 0x000F - Flip TX polarity on lane 0.
 * value of 0x00F0 - Flip TX polarity on lane 1.
 * value of 0x0F00 - Flip TX polarity on lane 2.
 * value of 0xF000 - Flip TX polarity on lane 3.
 */
#define spn_PHY_TX_POLARITY_FLIP  "phy_tx_polarity_flip"

/* Flip PHY lane RX polarity. See phy_tx_polarity_flip for values */
#define spn_PHY_RX_POLARITY_FLIP  "phy_rx_polarity_flip"

/* Flip PCS lane TX polarity. See phy_xaui_tx_polarity_flip for values */
#define spn_PHY_PCS_TX_POLARITY_FLIP  "phy_pcs_tx_polarity_flip"

/* Flip PCS lane RX polarity. See phy_xaui_tx_polarity_flip for values */
#define spn_PHY_PCS_RX_POLARITY_FLIP  "phy_pcs_rx_polarity_flip"

/* Transform CX4 pinout to Higig pinout on 5650x/5660x */
#define spn_CX4_TO_HIGIG  "cx4_to_higig"
/*
 * Set serdes device CX4 mode or Higig mode for 10G speed. 
 * Value TRUE is CX4 mode, FALSE is Higig mode.
 */
#define spn_10G_IS_CX4  "10g_is_cx4"

/* Control Active Laser Loss of light level. */
#define spn_FORCE_OPTRXLOSLVL  "force_optrxloslvl"
/*
 * The following optical controls manage to force various PHY signal on
 * BCM8703/4/5
 * Control Active Optical Enable output level.
 */
#define spn_FORCE_OPTTXENBLVL  "force_opttxenblvl"

/* Control Active Optical Reset output level. */
#define spn_FORCE_OPTTXRSTLVL  "force_opttxrstlvl"

/* Control Active Laser Bias Fault level. */
#define spn_FORCE_OPTBIASFLTLVL  "force_optbiasfltlvl"

/* Control Active Temperature level. */
#define spn_FORCE_OPTTEMPFLTLVL  "force_opttempfltlvl"

/* Control Active Laser Power Fault level. */
#define spn_FORCE_OPTPRFLTLVL  "force_optprfltlvl"

/* Control Active TX fault level. */
#define spn_FORCE_OPTTXFLLVL  "force_opttxfllvl"

/* Control Active RX fault level. */
#define spn_FORCE_OPTRXFLTLVL  "force_optrxfltlvl"

/* Control Active TX on level. */
#define spn_FORCE_OPTTXONLVL  "force_opttxonlvl"
/*
 * BCM5665 family debug mode - bypass MCU, allows diagnostics such as
 * loopback to be run without initializing the MCU (but requires small
 * packet sizes and counts).
 */
#define spn_BYPASS_MCU  "bypass_mcu"
/*
 * Allow external MDIO master access.  Otherwise, the switch device
 * is the MDIO master.
 */
#define spn_MDIO_EXTERNAL_MASTER  "mdio_external_master"
/*
 * Per-port phy LED control values (currently only used by 546x phy driver)
 * see 546x phy data sheets:
 * ledN_mode are LED selector values from phy reg 0x1x[011101, 01110]
 * led_ctrl is phy reg 0x1x[01001]
 */
#define spn_PHY_LED1_MODE  "phy_led1_mode"

/* See description of phy_led1_mode */
#define spn_PHY_LED2_MODE  "phy_led2_mode"

/* See description of phy_led1_mode */
#define spn_PHY_LED3_MODE  "phy_led3_mode"

/* See description of phy_led1_mode */
#define spn_PHY_LED4_MODE  "phy_led4_mode"

/* Control the LED function on 546x phy device. */
#define spn_PHY_LED_CTRL  "phy_led_ctrl"

/* select the multi-color LED display pattern on 546x phy device. */
#define spn_PHY_LED_SELECT  "phy_led_select"
/*
 * Per-port control of fiber signal detection (for 546x phys)
 * 	0	use the phy's default as signal detect
 * 	1	use PECL SD as signal detect (default on 5461)
 * 	4	use LED4 as signal detect (default on 5464)
 * 10	use EN_10B as signal detect
 * Negating value treats signal detect as loss of signal without
 * needing an external inverter on the board
 */
#define spn_PHY_FIBER_DETECT  "phy_fiber_detect"
/*
 * MCU properties are available to tune DDR memory interfaces on devices
 * with external packet buffers.  The device value controlled by each
 * property is indicated in that property.  Note that such devices
 * typically have multiple channels to the packet buffer memory, so these
 * properties may be configured with the base name to control all channels,
 * or with the suffix "_ch#" to configure a specific channel.
 * A channel-specific property value will override an existing non-channel
 * value for the appropriate channel.
 * Please refer to the device documentation for additional details.
 */

/* BCM566x/5x: MCU_CHN#_MODE.DRV_STR_0 */
#define spn_MCU_DRV_STR0  "mcu_drv_str0"

/* BCM566x/5x: MCU_CHN#_MODE.DRV_STR_1 */
#define spn_MCU_DRV_STR1  "mcu_drv_str1"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_CLASS_2 */
#define spn_MCU_PAD_DATA_CLASS2  "mcu_pad_data_class2"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_PAD_DRIVE */
#define spn_MCU_PAD_DATA_DRIVE  "mcu_pad_data_drive"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.DATA_PAD_SLEW */
#define spn_MCU_PAD_DATA_SLEW  "mcu_pad_data_slew"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_CLASS_2 */
#define spn_MCU_PAD_ADDR_CLASS2  "mcu_pad_addr_class2"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_PAD_DRIVE */
#define spn_MCU_PAD_ADDR_DRIVE  "mcu_pad_addr_drive"

/* BCM566x/5x: MCU_CHN#_PAD_CTL.ADDR_PAD_SLEW */
#define spn_MCU_PAD_ADDR_SLEW  "mcu_pad_addr_slew"

/* BCM566x/5x: MCU_CHN#_DELAY_CTL.DQI_ADJ_DIR */
#define spn_MCU_DELAY_DQI_ADJ_DIR  "mcu_delay_dqi_adj_dir"

/* BCM566x/5x: MCU_CHN#_DELAY_CTL.DQI_ADJ_VAL */
#define spn_MCU_DELAY_DQI_ADJ_VAL  "mcu_delay_dqi_adj_val"

/* BCM566x/5x: MCU_CHN#_DELAY_CTL.ADDR_ADJ_DIR */
#define spn_MCU_DELAY_ADDR_ADJ_DIR  "mcu_delay_addr_adj_dir"

/* BCM566x/5x: MCU_CHN#_DELAY_CTL.ADDR_ADJ_VAL */
#define spn_MCU_DELAY_ADDR_ADJ_VAL  "mcu_delay_addr_adj_val"

/* BCM5665 MCU 16bit DDR configuration */
#define spn_MCU_16BIT_DDR  "mcu_16bit_ddr"

/* Default speed that the port will initialize with */
#define spn_PORT_INIT_SPEED  "port_init_speed"

/* Default duplex mode the port will initialize with */
#define spn_PORT_INIT_DUPLEX  "port_init_duplex"

/* Default local advertisement settings for a port */
#define spn_PORT_INIT_ADV  "port_init_adv"

/* Default auto negotiation state of the port */
#define spn_PORT_INIT_AUTONEG  "port_init_autoneg"

/* PHY address of a port */
#define spn_PORT_PHY_ADDR  "port_phy_addr"

/* First part of a uniqe PHY identifier, if not specified in register */
#define spn_PORT_PHY_ID0  "port_phy_id0"

/* Second part of a uniqe PHY identifier, if not specified in register */
#define spn_PORT_PHY_ID1  "port_phy_id1"

/* Configures 3 additional MDIO addresses for the mux port with 8040 type phy */
#define spn_PORT_PHY_ADDR1  "port_phy_addr1"

/* MDIO Bus Property to select the MDIO access mechanism (CLAUSE22 / CLAUSE45) */
#define spn_PORT_PHY_CLAUSE  "port_phy_clause"

/* Enable MAC to check 802.3 frame length field */
#define spn_MAC_LENGTH_CHECK_ENABLE  "mac_length_check_enable"
/*
 * L2 table is DMAed into memory to search for entries to delete
 * when no hardware assists are available.  DMA is done in smaller
 * parts to minimize memory use.  Must be port of 2.
 */
#define spn_L2DELETE_CHUNKS  "l2delete_chunks"

/* Size of chunks to read at once while iterating over VLAN XLATE memory */
#define spn_VLANDELETE_CHUNKS  "vlandelete_chunks"
/*
 * BCM5665 family filter sizes
 * The FE port filters on 5665/50/55 may be configured for two mask/rule sizes
 * 256 rules and 16 masks (default)
 * 128 rules and 24 masks
 * Use this to select the 128/24 configuration for the chip.
 */
#define spn_FILTER_RESIZE  "filter_resize"
/*
 * Spread the XQs across all COSqs as dictated by the weight properties.
 * This will allow use of all COSqs. However, if some COSqs are later
 * disabled, the XQs allocated here to those disabled COSQs will be
 * unavailable for use.
 * This property configures all COSq identically.  To specify the value
 * for a single COSq, use the suffix "_cos#".  A COSq-specific value
 * will override an generic property value.
 */
#define spn_MMU_XQ_WEIGHT  "mmu_xq_weight"
/*
 * Configure per-XQ packet aging for the various COSQs. The shortest age
 * allowed by H/W is 250 microseconds. The longest age allowed is 7.162
 * seconds (7162 msec). The maximum ratio between the longest age and
 * the shortest(nonzero) age is 7:2.
 * This property configures all COSq identically.  To specify the value
 * for a single COSq, use the suffix "_cos#".  A COSq-specific value
 * will override an generic property value.
 */
#define spn_MMU_XQ_AGING  "mmu_xq_aging"
/*
 * On 568xx devices, the XPORT block defaults to XE ports.  Uncomment the
 * following line to change all ports to HG ports.  A specific bitmap
 * may be provided to select some XE and some HG ports, with the set
 * bits initialized to HG ports.  Note that HG and XE ports may be
 * exchanged through the bcm_port_encap_set API.
 */
#define spn_PBMP_XPORT_XE  "pbmp_xport_xe"
/*
 * Some BCM56xxx devices, such as the BCM568xx series, allow the XPORTs
 * to be configured as XE, HG, and GE ports.  XPORTs set in this bitmap
 * will be GE ports.
 */
#define spn_PBMP_XPORT_GE  "pbmp_xport_ge"
/*
 * Uncomment the following line instead to set all GE ports as regular
 * front panel Ethernet ports.
 */
#define spn_PBMP_GPORT_STACK  "pbmp_gport_stack"
/*
 * pbmp_loopback is used to specify if a HIGIG/HIGIG-LITE port is
 * configured as loopback port
 * Uncomment the following line instead to set all HIGIG/HIGIG-LITE ports as regular
 * front panel Ethernet ports.
 */
#define spn_PBMP_LOOPBACK  "pbmp_loopback"

/* Command memory controls */
#define spn_MEMCMD_TIMEOUT_USEC  "memcmd_timeout_usec"
#define spn_MEMCMD_INTR_ENABLE  "memcmd_intr_enable"
#define spn_IPFIX_INTR_ENABLE  "ipfix_intr_enable"
#define spn_L2MOD_DMA_INTR_ENABLE  "l2mod_dma_intr_enable"
/*
 * ER_SEER_CFG_NO_EXT
 * ER_SEER_CFG_L2_512_EXT
 * ER_SEER_CFG_LPM_256_EXT
 * ER_SEER_CFG_L4_192_EXT
 * ER_SEER_CFG_L4_96_EXT
 * ER_SEER_CFG_LPM_256_L4_128_EXT
 * ER_SEER_CFG_LPM_384_L4_64_EXT
 * ER_SEER_CFG_LPM_128_L4_64_EXT
 * ER_SEER_CFG_LPM_192_L4_32_EXT
 * ER_SEER_CFG_LPM_448_EXT
 * ER_SEER_CFG_LPM_896_EXT
 */
#define spn_SEER_EXT_TABLE_CFG  "seer_ext_table_cfg"

/* External TCAM type */
#define spn_SEER_EXT_TCAM_SELECT  "seer_ext_tcam_select"

/* All V6 */
#define spn_SEER_HOST_HASH_TABLE_CFG  "seer_host_hash_table_cfg"

/* All MYSTATION */
#define spn_SEER_MVL_HASH_TABLE_CFG  "seer_mvl_hash_table_cfg"

/* HSE tuning parameters generated by extt command */
#define spn_SEER_HSE_EM_LATENCY7  "seer_hse_em_latency7"

/* CSE tuning parameters generated by extt command */
#define spn_SEER_CSE_EM_LATENCY7  "seer_cse_em_latency7"
/*
 * 8704 and 8705 XFP clock
 * 8704 and 8705 can provide the clock for the XFPs (thus eliminating the need
 * for an external clock. By default we enable it, but if you are not using it,
 * it should be disabled.
 */
#define spn_PHY_XFP_CLOCK  "phy_xfp_clock"
/*
 * Per-port parameter indicating the only PHY is 56XXX SERDES directly
 * connected to a fiber module.  This is needed on boards which have
 * resistors configuration to bypass external 5434/5464.
 * SERDES is used automatically if no PHY is detected on the MDIO.
 */
#define spn_PHY_56XXX  "phy_56xxx"

/* Enable Loss Of Signal(LOS) function. 0 disable, 1 enable */
#define spn_PHY_RX_LOS  "phy_rx_los"

/* Invert PHYs LOS signal level. 0 not invert, 1 invert */
#define spn_PHY_RX_LOS_INVERT  "phy_rx_los_invert"

/* Enable the module absent signalling function. 0 disable, 1 enable */
#define spn_PHY_MOD_ABS  "phy_mod_abs"

/* Invert PHYs MOD_ABS signal level. 0 not invert, 1 invert */
#define spn_PHY_MOD_ABS_INVERT  "phy_mod_abs_invert"
#define spn_TCAM_RESET_USEC  "tcam_reset_usec"
/*
 * On BCM5660x devices, track end-to-end flow control on 64 modules of
 * 16 ports, instead of 32 modules of 32 ports.
 */
#define spn_E2E_64_MODULES  "e2e_64_modules"

/* Timeout vaule in microseconds for BCM5660x search engine initialization */
#define spn_SEER_INIT_TIMEOUT_USEC  "seer_init_timeout_usec"

/* Control to disable parity messages */
#define spn_PARITY_ENABLE  "parity_enable"

/* Set BCM5660x external packet buffer to 500 MHz instead of 600 MHz */
#define spn_PLL600_SLOWCLK  "pll600_slowclk"

/* For MCU Channel 0 only (0x2 for Channel 1 only) */
#define spn_MCU_CHANNEL_BITMAP  "mcu_channel_bitmap"

/* BCM5660x: MCU_CHN#_TIMING_32.TCRD */
#define spn_MCU_TCRD  "mcu_tcrd"

/* BCM5660x: MCU_CHN#_TIMING_32.TCWD */
#define spn_MCU_TCWD  "mcu_tcwd"

/* BCM5660x: MCU_CHN#_TIMING_32.TWL */
#define spn_MCU_TWL  "mcu_twl"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET_TX  "mcu_dll90_offset_tx"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET3  "mcu_dll90_offset3"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET2  "mcu_dll90_offset2"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET1  "mcu_dll90_offset1"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET0_QK  "mcu_dll90_offset0_qk"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_DLL90_OFFSET_QKB  "mcu_dll90_offset_qkb"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_OVRD_SM_EN  "mcu_ovrd_sm_en"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_PHASE_SEL  "mcu_phase_sel"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY2_3  "mcu_sel_early2_3"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY1_3  "mcu_sel_early1_3"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY2_2  "mcu_sel_early2_2"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY1_2  "mcu_sel_early1_2"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY2_1  "mcu_sel_early2_1"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY1_1  "mcu_sel_early1_1"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY2_0  "mcu_sel_early2_0"

/* MCU tuning parameters generated by extt command */
#define spn_MCU_SEL_EARLY1_0  "mcu_sel_early1_0"
/*
 * This setting may be used to change the number of LPM entries caches
 * when performing traversals of the tables.  Increasing this number
 * uses more memory for increased speed.
 */
#define spn_SEER_LPM_TRAVERSE_ENTRIES  "seer_lpm_traverse_entries"
/*
 * The maximum number of MMU/MCU initialization failures allowed before
 * aborting on XGS devices with external packet buffers.
 */
#define spn_MMU_RESET_TRIES  "mmu_reset_tries"
/*
 * The number of MMU DLL lock checks performed to insure that the interface
 * is stable on XGS devices with external packet buffers.
 */
#define spn_MMU_PLL_LOCK_TESTS  "mmu_pll_lock_tests"
#define spn_MCU_ODT_IMP_ENABLE  "mcu_odt_imp_enable"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET_TX  "ddr72_dll90_offset_tx"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET3  "ddr72_dll90_offset3"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET2  "ddr72_dll90_offset2"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET1  "ddr72_dll90_offset1"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET0_QK  "ddr72_dll90_offset0_qk"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_DLL90_OFFSET_QKB  "ddr72_dll90_offset_qkb"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_OVRD_SM_EN  "ddr72_ovrd_sm_en"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_PHASE_SEL  "ddr72_phase_sel"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY2_3  "ddr72_sel_early2_3"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY1_3  "ddr72_sel_early1_3"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY2_2  "ddr72_sel_early2_2"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY1_2  "ddr72_sel_early1_2"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY2_1  "ddr72_sel_early2_1"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY1_1  "ddr72_sel_early1_1"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY2_0  "ddr72_sel_early2_0"

/* HSE tuning parameters generated by extt command */
#define spn_DDR72_SEL_EARLY1_0  "ddr72_sel_early1_0"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_DLL90_OFFSET_TX  "qdr36_dll90_offset_tx"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_DLL90_OFFSET_QK  "qdr36_dll90_offset_qk"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_DLL90_OFFSET_QKB  "qdr36_dll90_offset_qkb"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_OVRD_SM_EN  "qdr36_ovrd_sm_en"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_PHASE_SEL  "qdr36_phase_sel"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_SEL_EARLY2_1  "qdr36_sel_early2_1"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_SEL_EARLY1_1  "qdr36_sel_early1_1"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_SEL_EARLY2_0  "qdr36_sel_early2_0"

/* CSE tuning parameters generated by extt command */
#define spn_QDR36_SEL_EARLY1_0  "qdr36_sel_early1_0"

/* BCAM tuning */
#define spn_SEER_TUNNEL_SAM  "seer_tunnel_sam"

/* Master device of shared external TCAM */
#define spn_EXT_TCAM_SHARING_MASTER  "ext_tcam_sharing_master"

/* Slave device of shared external TCAM */
#define spn_EXT_TCAM_SHARING_SLAVE  "ext_tcam_sharing_slave"
/*
 * The size in bytes of memory to be used when clearing a table using bulk
 * table operations.  The number of table entries cleared in one operation
 * will vary by table entry width.
 */
#define spn_MEM_CLEAR_CHUNK_SIZE  "mem_clear_chunk_size"

/* Clear tables using the fastest method supported by the device. */
#define spn_MEM_CLEAR_HW_ACCELERATION  "mem_clear_hw_acceleration"

/* Check for mem max override properties and reconfigure memories. */
#define spn_MEM_CHECK_MAX_OVERRIDE  "mem_check_max_override"
/*
 * For BCM5660x devices, determines whether the L2 multicast port bitmap
 * should be stored within the L2 table, rather than in a separate table.
 * May be helpful when external memory is used to increase L2 resources.
 */
#define spn_L2MC_IN_L2ENTRY  "l2mc_in_l2entry"

/* 8705 PHY supports both LAN and WAN mode. The default setting is LAN mode. */
#define spn_PHY_WAN_MODE  "phy_wan_mode"

/* 8705 PHY reference clock input selection. This should be set to TRUE in WAN mode. */
#define spn_PHY_XCLKSEL_OVRD  "phy_xclksel_ovrd"

/* Invert PCS TX output to PMD. Supported only on BCM8705 PHY. */
#define spn_PHY_TX_INVERT  "phy_tx_invert"

/* Invert PCS RX output to PMD. Supported only on BCM8705 PHY. */
#define spn_PHY_RX_INVERT  "phy_rx_invert"
/*
 * BCM5651x and BCM5632x devices allow the L2 table to be reduced to a
 * smaller size.  This value will be rounded up to provide the maximum
 * table index corresponding to a table size which is a power of 2.
 */
#define spn_L2_TABLE_SIZE  "l2_table_size"
/*
 * BCM5651x and BCM5632x devices allow the L3 table to be reduced to a
 * smaller size.  This value will be rounded up to provide the maximum
 * table index corresponding to a table size which is a power of 2.
 */
#define spn_L3_TABLE_SIZE  "l3_table_size"
/*
 * BCM5651x and BCM5632x devices allow the STG table to be reduced to a
 * smaller size.  This value will be rounded up to provide the maximum
 * table index corresponding to a table size which is a power of 2.
 */
#define spn_STG_TABLE_SIZE  "stg_table_size"

/* Total TCAM (CFP) entries could be used for the ROBO family. */
#define spn_BCM_FIELD_ENTRY_SZ  "bcm_field_entry_sz"

/* Unlock CFP key pattern for some ROBO family. */
#define spn_BCM_FIELD_KEY_PATTERN  "bcm_field_key_pattern"

/* VLAN id to be reserved for RCPU traffic */
#define spn_RCPU_VLAN  "rcpu_vlan"

/* Use OOB (out of band) channel for sending/receiving rcpu packets */
#define spn_RCPU_USE_OOB  "rcpu_use_oob"

/* Channel number to use during OOB (out of band) sending/receiving RCPU packets */
#define spn_RCPU_OOB_CHANNEL  "rcpu_oob_channel"
/*
 * Mac driver/unit to use
 * rcpu_oob_channel
 * Valid ports on which RCPU packets can be received by slave device.
 */
#define spn_RCPU_RX_PBMP  "rcpu_rx_pbmp"

/* switch port connected to slave RCPU device. */
#define spn_RCPU_PORT  "rcpu_port"

/* RCPU master unit. This is unit which is used to inject pkts to slave rcpu device. */
#define spn_RCPU_MASTER_UNIT  "rcpu_master_unit"

/* modid assigned to a slave RCPU unit in the system */
#define spn_RCPU_SLAVE_MODID  "rcpu_slave_modid"

/* modid assigned to a master RCPU unit in the system */
#define spn_RCPU_MASTER_MODID  "rcpu_master_modid"
#define spn_RCPU_HIGIG_PORT  "rcpu_higig_port"

/* Indication that a switch can be control through RCPU mechanism only */
#define spn_RCPU_ONLY  "rcpu_only"

/* Indication that RCPU unit is present on a device */
#define spn_PCI2EB_OVERRIDE  "pci2eb_override"

/* Set global default maximum number of entry moves for all dual hash tables */
#define spn_DUAL_HASH_RECURSE_DEPTH  "dual_hash_recurse_depth"

/* Set default maximum number of entry moves for dual hash L2 table */
#define spn_DUAL_HASH_RECURSE_DEPTH_L2X  "dual_hash_recurse_depth_l2x"

/* Set default maximum number of entry moves for dual hash vlan table */
#define spn_DUAL_HASH_RECURSE_DEPTH_VLAN  "dual_hash_recurse_depth_vlan"

/* Set default maximum number of entry moves for dual hash mpls table */
#define spn_DUAL_HASH_RECURSE_DEPTH_MPLS  "dual_hash_recurse_depth_mpls"

/* Set default maximum number of entry moves for dual hash egress vlan table */
#define spn_DUAL_HASH_RECURSE_DEPTH_EGRESS_VLAN  "dual_hash_recurse_depth_egress_vlan"

/* Set default maximum number of entry moves for all dual hash L3 tables */
#define spn_DUAL_HASH_RECURSE_DEPTH_L3X  "dual_hash_recurse_depth_l3x"

/* Enable IPv6 128b prefix LPM routes. */
#define spn_IPV6_LPM_128B_ENABLE  "ipv6_lpm_128b_enable"

/* Percentage of per-port cells usable before flow control starts */
#define spn_MMU_FLOW_PERCENT  "mmu_flow_percent"

/* Number of simultaneous senders to each port for flow control purposes */
#define spn_MMU_FLOW_FANIN  "mmu_flow_fanin"
/*
 * Percentage of per-port/per-cos packets used before
 * red packets will be dropped
 */
#define spn_MMU_RED_DROP_PERCENT  "mmu_red_drop_percent"
/*
 * Percentage of per-port/per-cos packets used before
 * yellow packets will be dropped
 */
#define spn_MMU_YELLOW_DROP_PERCENT  "mmu_yellow_drop_percent"
/*
 * Per-port/per-cos static reserved limit.
 * Rounded up from bytes to next cell size.
 * Remaining cells are put in dynamic pool.
 * If 0, then mmu_static_percent is used.
 */
#define spn_MMU_STATIC_BYTES  "mmu_static_bytes"
/*
 * Percentage of per-port/per-cos cells to
 * use as static reserved limit.
 * Remaining cells are put in dynamic pool.
 * Only used if mmu_static_bytes is 0.
 */
#define spn_MMU_STATIC_PERCENT  "mmu_static_percent"
/*
 * (1536 * 2)
 * offset from dynamic cell set limits for
 * reset (enable) limits.
 * Rounded up from bytes to next cell size.
 */
#define spn_MMU_RESET_BYTES  "mmu_reset_bytes"

/* Non-stack port overcommit factor for dynamic pool */
#define spn_MMU_OVERCOMMIT  "mmu_overcommit"

/* Stack port overcommit factor for dynamic pool */
#define spn_MMU_OVERCOMMIT_STACK  "mmu_overcommit_stack"
/*
 * On BCM56601 C0 devices, the valid bit of the L3 IPMC table may be used
 * instead as a hit bit.  In such a case, an invalid entry is judged by
 * empty L2 and L3 port bitmaps.
 */
#define spn_L3_IPMC_VALID_AS_HIT  "l3_ipmc_valid_as_hit"

/* ESM SRAM tuning result generated by extt command */
#define spn_EXT_SRAM_TUNING  "ext_sram_tuning"

/* ESM SRAM tuning statistics generated by extt command */
#define spn_EXT_SRAM_TUNING_STATS  "ext_sram_tuning_stats"

/* ESM SRAM tuning statistics generated by extt2 command */
#define spn_EXT_SRAM_TUNING2_STATS  "ext_sram_tuning2_stats"

/* ESM SRAM tuning result generated by extt command */
#define spn_EXT_SRAM_PVT  "ext_sram_pvt"

/* ESM TCAM tuning result generated by extt command */
#define spn_EXT_TCAM_TUNING  "ext_tcam_tuning"

/* ESM TCAM tuning statistics generated by extt command */
#define spn_EXT_TCAM_TUNING_STATS  "ext_tcam_tuning_stats"

/* ESM TCAM tuning result generated by extt command */
#define spn_EXT_TCAM_PVT  "ext_tcam_pvt"

/* Disable copying External L2 table into shadow copy */
#define spn_EXT_L2_SHADOW_DISABLE  "ext_l2_shadow_disable"

/* 72-bit external L2 forward table */
#define spn_EXT_L2_FWD_TABLE_SIZE  "ext_l2_fwd_table_size"

/* 72-bit external IPv4 forward table */
#define spn_EXT_IP4_FWD_TABLE_SIZE  "ext_ip4_fwd_table_size"

/* 72-bit external IPv6 64-bit prefix length forward table */
#define spn_EXT_IP6U_FWD_TABLE_SIZE  "ext_ip6u_fwd_table_size"

/* 144-bit external IPv6 128-bit prefix length forward table */
#define spn_EXT_IP6_FWD_TABLE_SIZE  "ext_ip6_fwd_table_size"

/* 288-bit external L2 ACL table */
#define spn_EXT_L2_ACL_TABLE_SIZE  "ext_l2_acl_table_size"

/* Number of entries in the 288-bit external L2 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_L2_ACL_TABLE_SCACHE_SIZE  "ext_l2_acl_table_scache_size"

/* 288-bit external IPv4 ACL table */
#define spn_EXT_IP4_ACL_TABLE_SIZE  "ext_ip4_acl_table_size"

/* Number of entries in the 288-bit external IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_IP4_ACL_TABLE_SCACHE_SIZE  "ext_ip4_acl_table_scache_size"

/* 360-bit external IPv6 ACL table */
#define spn_EXT_IP6S_ACL_TABLE_SIZE  "ext_ip6s_acl_table_size"

/* Number of entries in the 360-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_IP6S_ACL_TABLE_SCACHE_SIZE  "ext_ip6s_acl_table_scache_size"

/* 432-bit external IPv6 ACL table */
#define spn_EXT_IP6F_ACL_TABLE_SIZE  "ext_ip6f_acl_table_size"

/* Number of entries in the 432-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_IP6F_ACL_TABLE_SCACHE_SIZE  "ext_ip6f_acl_table_scache_size"

/* 144-bit external L2 ACL table */
#define spn_EXT_L2C_ACL_TABLE_SIZE  "ext_l2c_acl_table_size"

/* Number of entries in the 144-bit external L2 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_L2C_ACL_TABLE_SCACHE_SIZE  "ext_l2c_acl_table_scache_size"

/* 144-bit external IPv4 ACL table */
#define spn_EXT_IP4C_ACL_TABLE_SIZE  "ext_ip4c_acl_table_size"

/* Number of entries in the 144-bit external IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_IP4C_ACL_TABLE_SCACHE_SIZE  "ext_ip4c_acl_table_scache_size"

/* 144-bit external IPv6 ACL table */
#define spn_EXT_IP6C_ACL_TABLE_SIZE  "ext_ip6c_acl_table_size"

/* Number of entries in the 144-bit external IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_IP6C_ACL_TABLE_SCACHE_SIZE  "ext_ip6c_acl_table_scache_size"

/* 432-bit external L2 + IPv4 ACL table */
#define spn_EXT_L2IP4_ACL_TABLE_SIZE  "ext_l2ip4_acl_table_size"

/* Number of entries in the 432-bit external L2 + IPv4 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_L2IP4_ACL_TABLE_SCACHE_SIZE  "ext_l2ip4_acl_table_scache_size"

/* 432-bit external L2 + IPv6 ACL table */
#define spn_EXT_L2IP6_ACL_TABLE_SIZE  "ext_l2ip6_acl_table_size"

/* Number of entries in the 432-bit external L2 + IPv6 ACL table to reserve for use as warm-start scache.  If a value is not specified, no entries are reserved, and the regular external scache is used for level-2 warm start.  If a value is specified, that number of entries are reserved for use as the level-2 warm start scache.  If the value specified is 0, an optimal number of reserved entries is calculated such that the reserved space will hold all usable entries. */
#define spn_EXT_L2IP6_ACL_TABLE_SCACHE_SIZE  "ext_l2ip6_acl_table_scache_size"

/* ESM TCAM operating frequency */
#define spn_EXT_TCAM_FREQ  "ext_tcam_freq"

/* ESM TCAM mode, 0 for 6 cycles per packet, 1 for 4 cycles per packet */
#define spn_EXT_TCAM_MODE  "ext_tcam_mode"
#define spn_EXT_TCAM_DEV_TYPE  "ext_tcam_dev_type"

/* Number of TCAM banks in the ESM TCAM module */
#define spn_EXT_TCAM_BANKS  "ext_tcam_banks"

/* ESM SRAM operating frequency */
#define spn_EXT_SRAM_FREQ  "ext_sram_freq"

/* ESM SRAM mode, 0 for 1.5 clock latency, 1 for 2 clock latency */
#define spn_EXT_SRAM_MODE  "ext_sram_mode"
#define spn_EXT_SRAM_SPEED  "ext_sram_speed"
#define spn_EXT_SRAM0_PRESENT  "ext_sram0_present"
#define spn_EXT_SRAM1_PRESENT  "ext_sram1_present"
/*
 * External associated data mode:
 * 1: 250 MHz, L2 table in ES0
 * 2: 250 MHz, L2 table in ES1
 * 3: 250 MHz, L3 table in ES0
 * 4: 250 MHz, L3 table in ES1
 * 5: 250 MHz, L2 and L3 table in ES0
 * 6: 250 MHz, L2 and L3 table in ES1
 * 7: 334 MHz, ACL table in ES0
 * 8: 334 MHz, ACL table in ES1
 * 9: 250 MHz, ACL table in both ES0 and ES1
 * 10: 250 MHz, L2 and ACL table in both ES0 and ES1
 * 11: 250 MHz, L3 and ACL table in both ES0 and ES1
 * 12: 334 MHz, L2 and L3 and ACL table in both ES0 and ES1
 */
#define spn_EXT_AD_MODE  "ext_ad_mode"
/*
 * External IPv6 forwarding search key selection
 * 0 for 72-bit, 1 for 144-bit
 */
#define spn_EXT_IP6_FWD_KEY  "ext_ip6_fwd_key"
/*
 * External ACL search key selection for L2 packet
 * 0 for disable, 1 for 288-bit, 2 for 144-bit
 */
#define spn_EXT_L2_ACL_KEY  "ext_l2_acl_key"
/*
 * External ACL search key selection for IPv4 packet
 * 0 for disable, 1 for 288-bit, 2 for 144-bit, 3 for using both L2 and IP4 key,
 * 4 for using L2 key
 */
#define spn_EXT_IP4_ACL_KEY  "ext_ip4_acl_key"
/*
 * External ACL search key selection for IPV6 packet
 * 0 for disable, 1 for 360-bit, 2 for 432-bit, 3 for 144-bit,
 * 4 for using both L2 and IP6 key, 5 for using L2 key
 */
#define spn_EXT_IP6_ACL_KEY  "ext_ip6_acl_key"
/*
 * On BCM5662x devices, enable external TCAM lookup on XPORT block
 * (back-panel ports) instead of XGPORT block (front-panel ports)
 */
#define spn_EXT_LOOKUP_ON_XPORT  "ext_lookup_on_xport"
/*
 * Enable SGMII autonegotiation between the serdes and PHY if the 
 * serdes supports SGMII autonegotiation.
 */
#define spn_PHY_SGMII_AUTONEG  "phy_sgmii_autoneg"

/* Priority assigned to COS number 0 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS0  "rcpu_dot1pri_cos0"

/* Priority assigned to COS number 1 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS1  "rcpu_dot1pri_cos1"

/* Priority assigned to COS number 2 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS2  "rcpu_dot1pri_cos2"

/* Priority assigned to COS number 3 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS3  "rcpu_dot1pri_cos3"

/* Priority assigned to COS number 4 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS4  "rcpu_dot1pri_cos4"

/* Priority assigned to COS number 5 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS5  "rcpu_dot1pri_cos5"

/* Priority assigned to COS number 6 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS6  "rcpu_dot1pri_cos6"

/* Priority assigned to COS number 7 on a remote unit in RCPU system */
#define spn_RCPU_DOT1PRI_COS7  "rcpu_dot1pri_cos7"

/* Module Header Traffic Class value for COS number 0 */
#define spn_RCPU_MH_TC_COS0  "rcpu_mh_tc_cos0"

/* Module Header Traffic Class value for COS number 1 */
#define spn_RCPU_MH_TC_COS1  "rcpu_mh_tc_cos1"

/* Module Header Traffic Class value for COS number 2 */
#define spn_RCPU_MH_TC_COS2  "rcpu_mh_tc_cos2"

/* Module Header Traffic Class value for COS number 3 */
#define spn_RCPU_MH_TC_COS3  "rcpu_mh_tc_cos3"

/* Module Header Traffic Class value for COS number 4 */
#define spn_RCPU_MH_TC_COS4  "rcpu_mh_tc_cos4"

/* Module Header Traffic Class value for COS number 5 */
#define spn_RCPU_MH_TC_COS5  "rcpu_mh_tc_cos5"

/* Module Header Traffic Class value for COS number 6 */
#define spn_RCPU_MH_TC_COS6  "rcpu_mh_tc_cos6"

/* Module Header Traffic Class value for COS number 7 */
#define spn_RCPU_MH_TC_COS7  "rcpu_mh_tc_cos7"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 0 */
#define spn_RCPU_CPU_TC_COS0  "rcpu_cpu_tc_cos0"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 1 */
#define spn_RCPU_CPU_TC_COS1  "rcpu_cpu_tc_cos1"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 2 */
#define spn_RCPU_CPU_TC_COS2  "rcpu_cpu_tc_cos2"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 3 */
#define spn_RCPU_CPU_TC_COS3  "rcpu_cpu_tc_cos3"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 4 */
#define spn_RCPU_CPU_TC_COS4  "rcpu_cpu_tc_cos4"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 5 */
#define spn_RCPU_CPU_TC_COS5  "rcpu_cpu_tc_cos5"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 6 */
#define spn_RCPU_CPU_TC_COS6  "rcpu_cpu_tc_cos6"

/* CPU Traffic Class to be added to the remote CPU packet for COS number 7 */
#define spn_RCPU_CPU_TC_COS7  "rcpu_cpu_tc_cos7"

/* CPU queue id to be used for RCPU packets */
#define spn_RCPU_CPU_QUEUE  "rcpu_cpu_queue"

/* Pick up the Module Header SRC_PID value from the PBE bus for RCPU packets */
#define spn_RCPU_MH_SRC_PID_ENABLE  "rcpu_mh_src_pid_enable"

/* Add CPU Traffic Class to the RCPU packet */
#define spn_RCPU_MH_CPU_COS_ENABLE  "rcpu_mh_cpu_cos_enable"

/* Add Module Header Traffic Class to the RCPU packet */
#define spn_RCPU_MH_TC_MAP_ENABLE  "rcpu_mh_tc_map_enable"

/* COS Priority is enable on RCPU packet */
#define spn_RCPU_DOT1PRI_MAP_ENABLE  "rcpu_dot1pri_map_enable"
/*
 * On BCM5651x devices, select which of the 10G ports should be run in
 * single-lane serdes mode at 1/4 speed.  This bitmap consists of four
 * bits corresponding to the 10G ports.
 */
#define spn_LMD_ENABLE_PBMP  "lmd_enable_pbmp"

/* Number of IPFIX export entries allocated for the FIFO DMA host buffer */
#define spn_IPFIX_HOSTBUF_SIZE  "ipfix_hostbuf_size"

/* IPFIX export fifo thread priorities; 0 is highest and 255 is lowest */
#define spn_IPFIX_THREAD_PRI  "ipfix_thread_pri"

/* Set the Receive Status Vector (RSV) mask for the Unimac */
#define spn_GPORT_RSV_MASK  "gport_rsv_mask"

/* Enable post initialization for FE ports on BCM56024 and BCM56018 */
#define spn_POST_INIT_ENABLE  "post_init_enable"

/* Device that can support more than 32 ports per single modid will operate in configuration where all ports are mapped to the base modid */
#define spn_MODULE_64PORTS  "module_64ports"

/* All API will return port numbers in GPORT encodings */
#define spn_GPORT  "bcm_use_gport"
/*
 * Multicast ranges
 * The Higig2 header format concatenates the broadcast, multicast, and
 * IP multicast indices into one generic multicast index.  The mapping
 * between the individual indices and the combined index is specified by
 * these.  The default values are indicated.
 * This value sets the allowed range of broadcast indices in the Higig2
 * header for stack ports.
 */
#define spn_HIGIG2_MULTICAST_VLAN_RANGE  "higig2_multicast_vlan_range"
/*
 * Multicast ranges
 * This value sets the allowed range of multicast indices in the Higig2
 * header for stack ports.
 */
#define spn_HIGIG2_MULTICAST_L2_RANGE  "higig2_multicast_l2_range"
/*
 * Multicast ranges
 * This value sets the allowed range of IP multicast indices in the Higig2
 * header for stack ports.
 */
#define spn_HIGIG2_MULTICAST_L3_RANGE  "higig2_multicast_l3_range"

/* Uncomment the following line to make all HG ports default to HiGig2. */
#define spn_HIGIG2_HDR_MODE  "higig2_hdr_mode"
/*
 * In BCM568xx and BCM567xx devices, some L2 and L3 multicast
 * information is stored in a shared resource.  This value describes
 * the number of resource entries devoted to L2 multicast.
 */
#define spn_MULTICAST_L2_RANGE  "multicast_l2_range"
/*
 * In BCM568xx and BCM567xx devices, some L2 and L3 multicast
 * information is stored in a shared resource.  This value describes
 * the number of resource entries devoted to IP multicast.
 */
#define spn_MULTICAST_L3_RANGE  "multicast_l3_range"

/* Enable/Disable SLAM DMA */
#define spn_TSLAM_DMA_ENABLE  "tslam_dma_enable"

/* Enable/Disable TABLE DMA */
#define spn_TABLE_DMA_ENABLE  "table_dma_enable"

/* Enable/Disable CCM DMA */
#define spn_CCM_DMA_ENABLE  "ccm_dma_enable"
/*
 * The rate divisor/dividend properties allow a specific function clock
 * to be adjusted with respect to the device core clock.  If the core
 * clock speed is altered from the default, then use these settings to
 * tune the function clock to the required frequency range.
 * The calculation is (core clock) * dividend / divisor = (function clock).
 */

/* I2C clock rate divisor */
#define spn_RATE_I2C_DIVISOR  "rate_i2c_divisor"

/* I2C clock rate dividend */
#define spn_RATE_I2C_DIVIDEND  "rate_i2c_dividend"

/* Statistics DMA clock rate divisor */
#define spn_RATE_STDMA_DIVISOR  "rate_stdma_divisor"

/* Statistics DMA clock rate dividend */
#define spn_RATE_STDMA_DIVIDEND  "rate_stdma_dividend"

/* External MDIO clock rate divisor */
#define spn_RATE_EXT_MDIO_DIVISOR  "rate_ext_mdio_divisor"

/* External MDIO clock rate dividend */
#define spn_RATE_EXT_MDIO_DIVIDEND  "rate_ext_mdio_dividend"

/* Internal MDIO clock rate divisor */
#define spn_RATE_INT_MDIO_DIVISOR  "rate_int_mdio_divisor"

/* Internal MDIO clock rate dividend */
#define spn_RATE_INT_MDIO_DIVIDEND  "rate_int_mdio_dividend"
/*
 * Specifiers the priority
 * of the OAM thread
 */
#define spn_BCM_OAM_THREAD_PRI  "bcm_oam_thread_pri"

/* Specifies the port bitmap of the ports on which system snake should be skipped. */
#define spn_SS_IGNORE_PBMP  "ss_ignore_pbmp"
/*
 * On BCM5682x and BCM5672x devices, some of the switching logic may be
 * skipped to decrease traffic latency.  The three modes available are:
 * 0 - normal operation
 * 1 - Skip L3 switch logic
 * 2 - Skip L3 and FP switch logic
 */
#define spn_SWITCH_BYPASS_MODE  "switch_bypass_mode"
/*
 * Use a bulk memory operation when writing multiple table entries
 * in the CLI.
 */
#define spn_DIAG_SHELL_USE_SLAM  "diag_shell_use_slam"
#define spn_RLINK_L2_REMOTE_MAX  "rlink_l2_remote_max"
#define spn_RLINK_L2_LOCAL_MAX  "rlink_l2_local_max"
#define spn_RLINK_LINK_REMOTE_MAX  "rlink_link_remote_max"
#define spn_RLINK_LINK_LOCAL_MAX  "rlink_link_local_max"
#define spn_RLINK_AUTH_REMOTE_MAX  "rlink_auth_remote_max"
#define spn_RLINK_AUTH_LOCAL_MAX  "rlink_auth_local_max"
#define spn_RLINK_RX0_REMOTE_MAX  "rlink_rx0_remote_max"
#define spn_RLINK_RX1_REMOTE_MAX  "rlink_rx1_remote_max"
#define spn_RLINK_RX2_REMOTE_MAX  "rlink_rx2_remote_max"
#define spn_RLINK_RX3_REMOTE_MAX  "rlink_rx3_remote_max"
#define spn_RLINK_RX4_REMOTE_MAX  "rlink_rx4_remote_max"
#define spn_RLINK_RX5_REMOTE_MAX  "rlink_rx5_remote_max"
#define spn_RLINK_RX6_REMOTE_MAX  "rlink_rx6_remote_max"
#define spn_RLINK_RX7_REMOTE_MAX  "rlink_rx7_remote_max"

/* Specifies the max number of queued notifications in server side */
#define spn_RLINK_OAM_REMOTE_MAX  "rlink_oam_remote_max"

/* Specifies the max number of queued notifications in client side */
#define spn_RLINK_OAM_LOCAL_MAX  "rlink_oam_local_max"
/*
 * Enable diag shell port mapping. Port names will be assigned in
 * dport order, and the BCM shell will list multiple ports in
 * dport order regardless of the internal port numbering.
 */
#define spn_DPORT_MAP_ENABLE  "dport_map_enable"
/*
 * Port names for each port type (fe, ge, etc.) will increment
 * by one starting at zero, e.g. if a switch has four xe ports
 * with dport numbers 24, 25, 26, and 27, they will be named
 * xe0, xe1, xe2, and xe3. In non-indexed mode the ports would
 * be named xe24, xe25, xe26, and xe27.
 */
#define spn_DPORT_MAP_INDEXED  "dport_map_indexed"
/*
 * Traditionally, specifying a raw number instead of a port name
 * in the diag shell will be parsed as if port numbers are counted
 * from 1 up to the number of enabled ports. Typically this would
 * mean that for a gigabit switch, port 1 would correspond to ge0,
 * and so forth. Setting this flag causes raw port numbers to be
 * parsed as internal port numbers.
 */
#define spn_DPORT_MAP_DIRECT  "dport_map_direct"

/* Map dport number <dport> to internal port number <port>. dport_map_port_<port>=<dport> */
#define spn_DPORT_MAP_PORT  "dport_map_port"
/*
 * Interval (in usecs) at which the port monitor thread will run.
 * The port monitor can be used to handle workarounds which are
 * required only with specific equipment configurations.
 */
#define spn_PORTMON_INTERVAL  "portmon_interval"
/*
 * Select whether to always attach the corresponding Serdes shadow
 * driver for Raptor and Raven devices. Note that when deciding
 * which driver to attach, MDIO accesses are also verified independently
 * and checked for corruption. If corruption is detected, the
 * shadow driver is attached regardless of this property.
 * To always attach the shadow driver for a port:
 * serdes_shadow_driver_<port>=1
 */
#define spn_SERDES_SHADOW_DRIVER  "serdes_shadow_driver"
/*
 * Configure a BCM56725 device for 16-16G ports, instead of the default
 * 8-21G + 4-16G ports
 */
#define spn_BCM56725_16X16  "bcm56725_16x16"
/*
 * Configure a BCM56822 device for 8-16G + 12-10G + 4-1G ports, instead
 * of the default 4-21G + 2-16G + 12-10G + 4-1G ports
 */
#define spn_BCM56822_8X16  "bcm56822_8x16"
/*
 * Configure a BCM56821 device for 20-12G + 4-1G ports, instead
 * of the default 8-16G + 12-10G + 4-1G ports
 */
#define spn_BCM56821_20X12  "bcm56821_20x12"

/* L2 Caching of BPDU MAC addresses will be turned off */
#define spn_SKIP_L2_USER_ENTRY  "skip_L2_USER_ENTRY"

/* Enable Bigmac and Unimac on the XGPORT blocks of BCM56626 and BCM56628 */
#define spn_FLEX_XGPORT  "flex_xgport"

/* Enable the 40GE mode of BCM56629 */
#define spn_BCM56629_40GE  "bcm56629_40ge"

/* Enable the 28GE and 7x10G Higig mode of BCM56639 */
#define spn_BCM56639_28G_7X10  "bcm56639_28g_7x10"

/* Enable the 8x12G Higig mode (with loopback) of BCM56638 */
#define spn_BCM56638_8X12  "bcm56638_8x12"

/* Enable the 4x12G and 2x24G Higig mode (with loopback) of BCM56638 */
#define spn_BCM56638_4X12_2X24  "bcm56638_4x12_2x24"

/* Enable the 24GE and 6x12G Higig mode (with loopback) of BCM56636 */
#define spn_BCM56636_24G_6X12  "bcm56636_24g_6x12"

/* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56636 */
#define spn_BCM56636_2X12_2X24  "bcm56636_2x12_2x24"

/* Enable the 48GE and 4x12G Higig mode (with loopback) of BCM56634 */
#define spn_BCM56634_48G_4X12  "bcm56634_48g_4x12"

/* Enable the 48GE and 2x24G Higig mode (with loopback) of BCM56634 */
#define spn_BCM56634_48G_2X24  "bcm56634_48g_2x24"

/* Enable the 48GE and 4x12G Higig mode (with loopback) of BCM56538 */
#define spn_BCM56538_48G_4X12  "bcm56538_48g_4x12"

/* Enable the 48GE and 2x24G Higig mode (with loopback) of BCM56538 */
#define spn_BCM56538_48G_2X24  "bcm56538_48g_2x24"

/* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56630 */
#define spn_BCM56630_2X12_2X24  "bcm56630_2x12_2x24"

/* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56521 */
#define spn_BCM56521_2X12_2X24  "bcm56521_2x12_2x24"

/* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56524 */
#define spn_BCM56524_2X12_2X24  "bcm56524_2x12_2x24"

/* Enable the 24GE and 2x12G Higig and 2x24G Higig mode (with loopback) of BCM56534 */
#define spn_BCM56534_2X12_2X24  "bcm56534_2x12_2x24"

/* Enable the 28GE and 2x12G Higig and 4x16G Higig mode (with loopback) of BCM56526 */
#define spn_BCM56526_2X12_4X16  "bcm56526_2x12_4x16"
#define spn_BCM5614X_CONFIG  "bcm5614x_config"
#define spn_BCM5644X_CONFIG  "bcm5644x_config"

/* Enable the 12G Higig mode on BCM56630, BCM56521, BCM56522, BCM56524 or BCM56534 by setting the value to 12000 */
#define spn_HIGIG_MAX_SPEED  "higig_max_speed"
#define spn_FRONT_PANEL_ESM  "front_panel_esm"

/* L2 and VLAN module initialization will be skipped */
#define spn_SKIP_L2_VLAN_INIT  "skip_l2_vlan_init"
/*
 * Convenience variable that can be used to turn off both physical
 * and system port mapping. This variable overrides the dedicated
 * variables described above.
 */
#define spn_BCM_XLATE_PORT_ENABLE  "bcm_xlate_port_enable"
/*
 * Enable translation of physical port numbers within the BCM layer.
 * This feature allows a new device to emulate an older similar
 * device even if the physical port map is different. Note that
 * translation support must be compiled in as well.
 */
#define spn_BCM_XLATE_API_PORT_ENABLE  "bcm_xlate_api_port_enable"
/*
 * Enable translation of system port numbers to physical port numbers
 * in hardware (if supported by the switch device). This feature may
 * be used to complement the BCM API translation feature, but can
 * also be used to limit the use of module IDs on devices with 32 or
 * fewer ports in case some physical port numbers reside beyond 31.
 */
#define spn_BCM_XLATE_SYSPORT_ENABLE  "bcm_xlate_sysport_enable"

/* String identification of port mapping function to be used. */
#define spn_BCM_XLATE_PORT_MAP  "bcm_xlate_port_map"

/* Indication if the port should be remapped given a mapping function */
#define spn_BCM_XLATE_PORT  "bcm_xlate_port"

/* Configure the PHY address(es) for the flex-ports */
#define spn_FLEX_PORT_PHY_ADDR  "flex_port_phy_addr"
/*
 * Display the usage information for a CLI command when "help <cmd>",
 * "? <cmd>", or "<cmd> {unrecognized parameters}" is entered.  To suppress
 * the usage message, set this property to 0.
 */
#define spn_HELP_CLI_ENABLE  "help_cli_enable"
/*
 * Display table information when the "listmem" CLI command is used.
 * To suppress the table listing, set this property to 0.
 */
#define spn_MEMLIST_ENABLE  "memlist_enable"
/*
 * Display register information when the "listreg" CLI command is used.
 * To suppress the register listing, set this property to 0.
 */
#define spn_REGLIST_ENABLE  "reglist_enable"

/* Enable lane0 IEEE MII reset on Hyperlite/Hypercore serdes. */
#define spn_SERDES_LANE0_RESET  "serdes_lane0_reset"

/* BCM5321 / BCM5320 Selection */
#define spn_PBMP_FE_100FX  "pbmp_fe_100fx"
/*
 * Specify the group numbers which could be supported in the INGRESS stage for the ROBO family.
 * In ROBO FP architecture, all entries are shared for all slices. Group numbers are not
 * limited by slice numbers. TCAM_SLICE could be used to specify the group numbers for the ROBO family.
 */
#define spn_ROBO_INGRESS_TCAM_SLICE  "robo_ingress_tcam_slice"

/* Specify the group numbers which could be supported in the EGRESS stage for the ROBO family. */
#define spn_ROBO_EGRESS_TCAM_SLICE  "robo_egress_tcam_slice"

/* Specify the group numbers which could be supported in the LOOKUP stage for the ROBO family. */
#define spn_ROBO_LOOKUP_TCAM_SLICE  "robo_lookup_tcam_slice"
/*
 *  BCM5321 / BCM5320 Selection
 * Select either BCM5321 or BCM5320(16 / 8 ports of BCM5324 family)
 * It is BCM5321
 */
#define spn_BCM5321  "bcm5321"

/* It is BCM5320 */
#define spn_BCM5320  "bcm5320"
/*
 * Specifies the Logical to physical port mapping and bandwidth allocation.
 * portmap_<port>=<physical port number>:<bandwidth in Gb>\[:<queue config>\].
 * Applicable to BCM56840 and BCM56740 device family
 */
#define spn_PORTMAP  "portmap"
/*
 * SBX properties
 * UCODE Port Properties
 * 
 * The following properties are for FE to convey mapping
 * from microcode port to physical port.
 * 
 *    ucode_num_ports - defines the maximum number of microcode visible
 *                      ports on any module.
 * 
 *    ucode_port_<number> = <b-type><b-num>[.<b-port>:<s-type><s-num>.<s-port>]
 * 
 *  where,
 *    <b-type> is the front-panel block type: ge, xe, spi, pci
 *    <b-num>  is the front-panel block number (0-1)
 *    <b-port> is the front-panel port number (within the block)
 *    <s-type> is the system-side block type: spi
 *    <s-num>  is the system-side block number (0-1)
 *    <s-port> is the system-side port number (within the block)
 * 
 *  Notes:
 *  Mapping for a SPI bus port or PCI port should only contain the
 *  fields <b-type> and <b-num>.
 * 
 *  Examples:
 *    ucode_num_ports.1    = 32
 *    ucode_port.port1.1   = ge0.0:spi1.0    <-- Front panel GE port
 *    ucode_port.port27.1  = spi0.0:spi1.1   <-- Front panel SPI subport
 *    ucode_port.port31.1  = spi0            <-- SPI port (for SPI0)
 *    ucode_port.port32.1  = pci0            <-- CPU port
 */
#define spn_UCODE_NUM_PORTS  "ucode_num_ports"
#define spn_UCODE_PORT  "ucode_port"

/* Block types for ucode port property <b-type> <s-type> */
#define spn_UCODE_PORT_TYPE_GE  "ge"
#define spn_UCODE_PORT_TYPE_XE  "xe"
#define spn_UCODE_PORT_TYPE_SPI  "spi"
#define spn_UCODE_PORT_TYPE_PCI  "pci"
#define spn_UCODE_PORT_TYPE_HG  "hg"
/*
 * This property is valid on FE
 * It selects a particular packet buffer for a port
 */
#define spn_PORT_PB_SELECT  "pb_select"

/* bcm_rx parses out the sbx Egress Route header when set */
#define spn_RX_PARSE_ERH  "rx_parse_erh"

/* defines the number of FTEs used for local gports, default: SBX_MAX_GPORTS */
#define spn_FTE_NUM_LOCAL_GPORTS  "fte_num_local_gports"
/*
 *  Following properties are global
 *    spn_FABRIC_CONFIGURATION
 *       - fabric mode
 *         0: DMode (qe2000 + bm3200 system)
 *         1:
 *         2:
 *    spn_MTU_SIZE
 *       - MTU size in bytes used for wred calculation
 *    spn_BIST_ENABLE
 *       - 0: not run self test, 1: run self test
 *    spn_HALF_BUS_MODE
 *       - 0: full-bus mode system, 1: half-bus mode system
 *    spn_ACTIVE_SWITCH_CONTROLLER_ID
 *       - 0: Switch controller 0 is active, 1: Switch controller 1 is active
 *    spn_REDUNDANCY_MODE
 *       - 0:     manual mode
 *         1:     1+1 control and data plane
 *         2:     1+1 control and Load sharing data plane
 *         3:     1+1 control and Enhanced Load sharing data plane
 *         4:     Load sharing data plane
 *         5:     Enhanced load sharing data plane
 *    spn_MAX_FAILED_LINKS
 *       - max number of failed links before QE is mapped out, used for
 *         load sharing data plane redundancy mode
 *    spn_HYBRID_MODE
 *       - System configuration is Hybrid mode. 1 indicates hybrid mode
 *    spn_NUM_MAX_FABRIC_PORTS_ON_MODULE
 *       - maximim fabric ports on any module. Required for Hybrid mode.
 *       - Required on each FE for all modes; must be set to the maximum number
 *         of fabric ports on any one line card present in the system.
 *    spn_NUM_MIN_FABRIC_PORTS_ON_MODULE
 *       - minimum fabric ports on any module. Required for Hybrid mode.
 *    spn_ARBPORT_ALLOC_MODE
 *    spn_QE_TME_MODE
 *       - specifies if the QE is running in TME mode.
 *         1 means TME
 *         2 means Hybrid
 *         3 means TME bypass  (Sportster)
 * 
 *  Following properties are global but required for sirius and polaris only
 *    spn_40G_PIPE_MODE
 *    spn_BACKPLANE_SERDES_SPEED
 *    spn_BACKPLANE_SERDES_ENCODING
 * 
 *    spn_SCI_PORT_MODID
 *       - specifies the modid associated with a SCI port
 * 
 */
#define spn_FABRIC_CONFIGURATION  "fabric_configuration"
#define spn_DISCARD_MTU_SIZE  "discard_mtu_size"
#define spn_DISCARD_QUEUE_SIZE  "discard_queue_size"
#define spn_BIST_ENABLE  "bist_enable"
#define spn_HALF_BUS_MODE  "half_bus_mode"
/*
 * backplane serdes speed. Supported on SBX fabric
 * 
 * 3125: 3.125 GHz
 * 6250: 6.250 GHz
 * 6500: 6.500 GHz
 */
#define spn_BACKPLANE_SERDES_SPEED  "backplane_serdes_speed"
/*
 * backplane serdes encoding. Supported on SBX fabric
 * 
 * 1: 8b10b encoding
 * 0: 64b66b encoding
 */
#define spn_BACKPLANE_SERDES_ENCODING  "backplane_serdes_encoding"
#define spn_ACTIVE_SWITCH_CONTROLLER_ID  "active_switch_controller_id"
#define spn_REDUNDANCY_MODE  "redundancy_mode"
#define spn_MAX_FAILED_LINKS  "max_failed_links"
#define spn_QE_TME_MODE  "qe_tme_mode"
#define spn_HOLD_PRI_NUM_TIMESLOTS  "hold_pri_num_timeslots"
#define spn_HYBRID_MODE  "hybrid_mode"
#define spn_NUM_MAX_FABRIC_PORTS_ON_MODULE  "num_max_fabric_ports_on_module"

/* Maximum number of SFI links used to connect to a QE2K device */
#define spn_QE2K_LINKS  "qe2k_links"

/* Maximum number of SFI links used to connect to a Sirius device */
#define spn_SIRIUS_LINKS  "sirius_links"
#define spn_SCI_PORT_MODID  "sci_port_modid"
/*
 * L2 Aging Cycles
 * 
 * Indicates the number of cycles in an L2 aging interval.  This value
 * affects the number of L2 entries to be processed by the aging engine
 * during a run.
 * A value of 1 results in processing the entire L2 table during
 * an age run cycle.
 */
#define spn_L2_AGE_CYCLES  "l2_age_cycles"

/* Run s/w based L2 ageing thread by default */
#define spn_RUN_L2_SW_AGEING  "run_l2_sw_ageing"

/* Defines the maximum number of l2 cache entries */
#define spn_L2CACHE_MAX  "l2cache_max_idx"
/*
 * On SBX QE devices Local McGroup resources start from the following index.
 *     - VLANS McGroup  => 0-4095
 *     - Global McGroup => 4096 - (value indicated by (spn_MC_GROUP_LOCAL_START_INDEX - 1))
 *     - Local McGroup  => (value indicated by spn_MC_GROUP_LOCAL_START_INDEX) - (max device limit)
 */
#define spn_MC_GROUP_LOCAL_START_INDEX  "mcast_group_local_start_index"
#define spn_PORT_IS_SCI  "port_is_sci"
#define spn_PORT_IS_SFI  "port_is_sfi"
#define spn_LINK_THRESHOLD  "link_threshold"
#define spn_LINK_DRIVER_STRENGTH  "link_driver_strength"
#define spn_LINK_DRIVER_EQUALIZATION  "link_driver_equalization"
/*
 * Following properties are valid on QE only
 *   spn_NUM_MODULES
 *      - specifies the number of QEs in the system
 *   spn_NUM_MODULES_00_31_MASK
 *      - mask of queues with module/node 00 - 31
 *   spn_NUM_MODULES_32_63_MASK
 *      - mask of queues with module/node 32 - 63
 *   spn_NUM_MODULES_64_95_MASK
 *      - mask of queues with module/node 64 - 95
 *   spn_SPI_0_REF_CLOCK_SPEED
 *      - Reference Clock speed in KHz for SPI port 0.
 *   spn_SPI_0_CLOCK_SPEED
 *      - Clock speed specified in KHz for SPI port 0.
 *   spn_SPI_1_REF_CLOCK_SPEED
 *      - Reference Clock speed in KHz for SPI port 1.
 *   spn_SPI_1_CLOCK_SPEED
 *      - Clock speed specified in KHz for SPI port 1.
 *   spn_QE_SPI_0_SUBPORTS
 *      - specifies the number of sub-ports on SPI port 0
 *   spn_QE_SPI_1_SUBPORTS
 *      - specifies the number of sub-ports on SPI port 1
 *   spn_SPI_0_NUM_TX_SUBPORTS
 *      - specifies the number of Tx sub-ports on SPI port 0
 *        If not specified this defaults to the value of spn_QE_SPI_0_SUBPORTS.
 *        The SPI calender is set for these number of ports. The SPI "cal_length"
 *        configuration is set to a value one less then the number of ports.
 *   spn_SPI_0_NUM_RX_SUBPORTS
 *      - specifies the number of Rx sub-ports on SPI port 0
 *        If not specified this defaults to the value of spn_QE_SPI_0_SUBPORTS.
 *        The SPI calender is set for these number of ports. The SPI "cal_length"
 *        configuration is set to a value one less then the number of ports.
 *   spn_SPI_1_NUM_TX_SUBPORTS
 *      - specifies the number of Tx sub-ports on SPI port 1
 *        If not specified this defaults to the value of spn_QE_SPI_1_SUBPORTS.
 *        The SPI calender is set for these number of ports. The SPI "cal_length"
 *        configuration is set to a value one less then the number of ports.
 *   spn_SPI_1_NUM_RX_SUBPORTS
 *      - specifies the number of Rx sub-ports on SPI port 1
 *        If not specified this defaults to the value of spn_QE_SPI_1_SUBPORTS.
 *        The SPI calender is set for these number of ports. The SPI "cal_length"
 *        configuration is set to a value one less then the number of ports.
 *   spn_SPI_0_TX_CAL_STATUS_REP_CNT
 *      - specifies Tx cal_m for SPI Port 0
 *        This is the repeatition count for status. This value maps directly to SPI
 *        "cal_m" configuraton.
 *   spn_SPI_0_RX_CAL_STATUS_REP_CNT
 *      - specifies Rx cal_m for SPI Port 0
 *        This is the repeatition count for status. This value maps directly to SPI
 *        "cal_m" configuraton.
 *   spn_SPI_1_TX_CAL_STATUS_REP_CNT
 *      - specifies Tx cal_m for SPI Port 1
 *        This is the repeatition count for status. This value maps directly to SPI
 *        "cal_m" configuraton.
 *   spn_SPI_1_RX_CAL_STATUS_REP_CNT
 *      - specifies Rx cal_m for SPI Port 0
 *        This is the repeatition count for status. This value maps directly to SPI
 *        "cal_m" configuraton.
 *   spn_QE_SPI_0_SUBPORT_SPEED
 *      - specifies the SPI 0 subport speed in Mbps
 *        if not specified, default to 1Gbps if spn_QE_SPI_0_SUBPORTS
 *        has more than 1 subport, otherwise default to 10 Gbps
 *   spn_QE_SPI_1_SUBPORT_SPEED
 *      - specifies the SPI 1 subport speed in Mbps
 *        if not specified, default to 1Gbps if spn_QE_SPI_1_SUBPORTS
 *        has more than 1 subport, otherwise default to 10 Gbps
 *   spn_QE_SPI_0_SUBPORT_IS_REQUEUE
 *      - specifies the SPI 0 subport is in requeue mode (for hybrid mode)
 *   spn_QE_SPI_1_SUBPORT_IS_REQUEUE
 *      - specifies the SPI 1 subport is in requeue mode (for hybrid mode)
 *   spn_QE_MEMORY_PART
 *      - specifies the memory part
 *        0:256mb DDR2 memory   , 2: 512mb DDR2 memory
 *   spn_QE_MAX_ARRIVAL_RATE
 *      - max arrival rate in Mbps
 *   spn_QE_CLOCK_SPEED
 *      - qe device clock speed in Mhz
 *   spn_QE_LONG_DDR_MEMTEST
 *      -
 *   spn_QE_2_5GBPS_LINKS
 *      -
 *   spn_QE_EG_MVT_SIZE
 *      - Number of MVT entries. Valid range (0,1,2)
 *        0: 12k entries.  1: 24k entries.  2: 48k entries
 *   spn_QE_MVR_MAX_SIZE
 *      - Maximum size of MVR in MDB elements.  Valid range = [1..5]
 *   spn_QE_EG_MC_DROP_ON_FULL
 *      -
 *   spn_QE_EI_PORT_TIMEOUT
 *      -
 *   spn_QE_GLOBAL_SHAPING_ADJUST
 *      -
 *   spn_QE_EGR_SHAPING_ADJUST
 *      - port or global parameter on Sirius units
 *        From Sirius specs: cell length adjustment.  It is an unsigned
 *        positive value added to cell length at packet SOP.
 *        Valid range is 0..31
 *   spn_QE_MIX_HIGH_LOW_RATE_FLOWS
 *      -
 *   spn_QE_SPI_0_FULL_PACKET_MODE
 *      - SPI 0 interface full packet mode
 *        0: Burst Interleaved
 *        1: Packet Interleaved, N:1 channel sharing mode
 *        2: Packet interleaved, full packet mode
 *   spn_QE_SPI_1_FULL_PACKET_MODE
 *      - SPI 1 interface full packet mode
 *        0: Burst Interleaved
 *        1: Packet Interleaved, N:1 channel sharing mode
 *        2: Packet interleaved, full packet mode
 *   spn_SPI_0_EI_LINES
 *      - Maximum of lines to use in EI buffer for port 0
 *   spn_SPI_1_EI_LINES
 *      - Maximum of lines to use in EI buffer for port 1
 *   spn_QE_QUEUES_PER_INGRESS_SHAPER
 *      - Number of queues for each ingress shaper. Valid Range(1,4,8,16)
 *   spn_QE_SC_TXDMA_SOT_DELAY_CLOCKS
 *      -
 *   spn_QE_SFI_TIMESLOT_OFFSET_CLOCKS
 *      -
 *   spn_QE_EP_DISABLE                 "qe_ep_disable"
 *      - Set to 1 to disable EP
 *   spn_QE_ERH_TYPE                   "qe_erh_type"
 *      - Set to 0 for C2-QE2K native G2P3 
 *      - Set to 1 for C2-Sirius header format
 *      - Set to 2 for C2-QE2K-Sirius interop header format
 *   spn_QE_MVT_FORMAT                 "qe_mvt_format"
 *      - Indicates EP format (MVTDA, MVTDB), Reference "encap_id" parameter
 *        of multicast Group API.
 *        0 -> Format required by gu2k, 1 -> 0-13 bits are mvtda, and 14-17 bits are mvtdb
 *   spn_QE_GRANT_OFFSET               "qe_grant_offset"
 *      - Number of clock cycles to wait after Start of Timeslot signal.
 *        Valid range (0-31), Default to 0xE
 *   spn_EGRESS_MC_EF_TIMEOUT
 *      - Timeout specified in micro-seconds
 *        A value of 0 indicates no timeout
 *   spn_EGRESS_MC_NEF_TIMEOUT
 *      - Timeout specified in micro-seconds
 *        A value of 0 indicates no timeout
 *   spn_EGRESS_FIFO_INDEPENDENT_FC
 *      - Egress FIFO independent flow control, 1 -> single bit full status mode,
 *                                              0 -> double bit full status mode
 *   spn_UNICAST_QUEUE_RESOURCE_ALLOCATION_MODE
 *      - Egress queue resource managment,      1 -> Do not allocate sysport and fcd
 *                                              0 -> Allocate sysport and fcd
 *   spn_DEMAND_SCALE
 *      - Scaling factor during bandwidth management to achieve better accuracy
 *                                              0 -> no scale
 *                                              n -> scale down 2^n
 *   spn_BCM_COSQ_SP_MODE
 *      - Specifies the Strict Priority (SP) mode. Following are the options
 *        0 -> SP is in BAG (BME) and queue type (on QE) indicates Hungry/Satisfied protocol.
 *        1 -> SP is in BAG (BME) for accounting purposes and queue Type (on QE) indicates
 *             Global SP.
 * 
 *   spn_FABRIC_CONNECT_MIN_UTILIZATION
 *      - Fabric minimum utilization (anemic watermark setting). this is specified
 *        as a percentage.
 *   spn_FABRIC_CONNECT_MAX_AGE_TIME
 *      - Fabric conection age time (anemic age timeout). This is specified
 *        in micro-seconds.
 *   spn_FABRIC_QOS_OPTIMIZE
 *      - QoS optimization.
 *        0 -> no optimization
 *        1 -> optimization
 */
#define spn_CORE_CLOCK_SPEED  "core_clock_speed"
#define spn_NUM_MODULES  "num_modules"
#define spn_NUM_MODULES_00_31_MASK  "num_modules_00_31_mask"
#define spn_NUM_MODULES_32_63_MASK  "num_modules_32_63_mask"
#define spn_NUM_MODULES_64_95_MASK  "num_modules_64_95_mask"
#define spn_SPI_0_REF_CLOCK_SPEED  "spi_0_ref_clock_speed"
#define spn_SPI_0_CLOCK_SPEED  "spi_0_clock_speed"
#define spn_SPI_1_REF_CLOCK_SPEED  "spi_1_ref_clock_speed"
#define spn_SPI_1_CLOCK_SPEED  "spi_1_clock_speed"
#define spn_QE_SPI_0_SUBPORTS  "qe_spi_0"
#define spn_QE_SPI_1_SUBPORTS  "qe_spi_1"
#define spn_SPI_0_NUM_TX_SUBPORTS  "spi_0_num_tx_subports"
#define spn_SPI_0_NUM_RX_SUBPORTS  "spi_0_num_rx_subports"
#define spn_SPI_1_NUM_TX_SUBPORTS  "spi_1_num_tx_subports"
#define spn_SPI_1_NUM_RX_SUBPORTS  "spi_1_num_rx_subports"
#define spn_SPI_0_TX_CAL_STATUS_REP_CNT  "spi_0_tx_cal_status_rep_cnt"
#define spn_SPI_0_RX_CAL_STATUS_REP_CNT  "spi_0_rx_cal_status_rep_cnt"
#define spn_SPI_1_TX_CAL_STATUS_REP_CNT  "spi_1_tx_cal_status_rep_cnt"
#define spn_SPI_1_RX_CAL_STATUS_REP_CNT  "spi_1_rx_cal_status_rep_cnt"
#define spn_SPI_INTERLEAVE_BURST_SIZE  "spi_interleave_burst_size"
#define spn_QE_SPI_0_SUBPORT_SPEED  "qe_spi_0_subport_speed"
#define spn_QE_SPI_1_SUBPORT_SPEED  "qe_spi_1_subport_speed"
#define spn_QE_SPI_0_SUBPORT_IS_REQUEUE  "qe_spi_0_subport_is_requeue"
#define spn_QE_SPI_1_SUBPORT_IS_REQUEUE  "qe_spi_1_subport_is_requeue"
#define spn_QE_HALF_BUS_MODE  "qe_half_bus_mode"
#define spn_QE_MEMORY_PART  "qe_memory_part"
#define spn_QE_MAX_ARRIVAL_RATE  "qe_max_arrival_rate"
#define spn_QE_CLOCK_SPEED  "qe_clock_speed"
#define spn_QE_LONG_DDR_MEMTEST  "qe_long_ddr_memtest"
#define spn_QE_2_5GBPS_LINKS  "qe_2_5gbps_links"
#define spn_QE_EG_MVT_SIZE  "qe_eg_mvt_size"

/* Specify dense-mode MVR size on devices that have variable-size MVR support. */
#define spn_QE_MVR_MAX_SIZE  "qe_mvr_max_size"

/* Nonzero to set dual-lookup mode for multicast, where OI translation space is split, providing an encapId and a Subscriber lookup per replicant. */
#define spn_QE_MC_DUAL_LOOKUP  "qe_mc_dual_lookup"

/* Nonzero to have the device redistribute unicast frames across aggregates based upon LBID, overriding the front-panel device distribution decision. */
#define spn_QE_LAG_UC_REDIST  "qe_lag_uc_redist"
#define spn_QE_EG_MC_DROP_ON_FULL  "qe_eg_mc_drop_on_full"
#define spn_QE_EI_PORT_TIMEOUT  "qe_ei_port_timeout"
#define spn_QE_ERH_TYPE  "qe_erh_type"
#define spn_QE_GLOBAL_SHAPING_ADJUST  "qe_global_shaping_adjust"
#define spn_QE_EGR_SHAPING_ADJUST  "qe_egr_shaping_adjust"
#define spn_QE_MIX_HIGH_LOW_RATE_FLOWS  "qe_mix_high_low_rate_flows"
#define spn_QE_SPI_0_FULL_PACKET_MODE  "qe_spi_0_full_packet_mode"
#define spn_QE_SPI_1_FULL_PACKET_MODE  "qe_spi_1_full_packet_mode"
#define spn_QE_SPI_0_EI_LINES  "qe_spi_0_ei_lines"
#define spn_QE_SPI_1_EI_LINES  "qe_spi_1_ei_lines"
#define spn_QE_QUEUES_PER_INGRESS_SHAPER  "qe_queues_per_ingress_shaper"
#define spn_QE_SC_TXDMA_SOT_DELAY_CLOCKS  "qe_sc_txdma_sot_delay_clocks"
#define spn_QE_SFI_TIMESLOT_OFFSET_CLOCKS  "qe_sfi_timeslot_offset_clocks"
#define spn_QE_EP_DISABLE  "qe_ep_disable"
#define spn_QE_MVT_FORMAT  "qe_mvt_format"
#define spn_QE_GRANT_OFFSET  "qe_grant_offset"
#define spn_EGRESS_MC_EF_TIMEOUT  "egress_mc_ef_timeout"
#define spn_EGRESS_MC_NEF_TIMEOUT  "egress_mc_nef_timeout"
#define spn_EGRESS_FIFO_INDEPENDENT_FC  "egress_fifo_independent_fc"
#define spn_UNICAST_QUEUE_RESOURCE_ALLOCATION_MODE  "unicast_queue_resource_allocation_mode"
#define spn_DEMAND_SCALE  "demand_scale"
#define spn_BCM_COSQ_SP_MODE  "bcm_cosq_sp_mode"
#define spn_IF_SUBPORTS  "if_subports"
#define spn_IF_SUBPORTS_CREATE  "if_subports_create"
/*
 * When set to 1, SDK setup the child gport ingress scheduler hierarchy
 * When set to 0, Application code is required to explicitly hook up 
 *                child gport in the ingress scheduler hierarchy
 */
#define spn_TM_FABRIC_PORT_HIERARCHY_SETUP  "tm_fabric_port_hierarchy_setup"
/*
 * When set to 1, SDK setup the child gport egress scheduler hierarchy
 * When set to 0, Application code is required to explicitly hook up 
 *                child gport in the egress scheduler hierarchy
 */
#define spn_ES_FABRIC_PORT_HIERARCHY_SETUP  "es_fabric_port_hierarchy_setup"
#define spn_IF_PROTOCOL  "if_protocol"
#define spn_FABRIC_EGRESS_SETUP  "fabric_egress_setup"
#define spn_FABRIC_CONNECT_MIN_UTILIZATION  "fabric_connect_min_utilization"
#define spn_FABRIC_CONNECT_MAX_AGE_TIME  "fabric_connect_max_age_time"
#define spn_FABRIC_QOS_OPTIMIZE  "fabric_qos_optimize"
#define spn_QE_MVT_OLD_CONFIGURATION  "qe_mvt_old_configuration"
/*
 * Supported only on QE2000. 4 FIFO Model. The first two are depricated.
 *    0: Multicast, Unicast EF, Unicast NEF
 *    1: Unicast EF, Multicast, Unicast NEF (Default for Multcast EF)
 *    2: Unicast EF, Unicast NEF, Multicast (Default for Multicast NEF)
 *  Multicast EF has higher priority then Mulicast NEF.
 */
#define spn_QE_HI_MC_PRIORITY  "qe_hi_mc_priority"
#define spn_QE_LO_MC_PRIORITY  "qe_lo_mc_priority"
#define spn_QE_THRESH_DROP_LIMIT  "qe_thresh_drop_limit"
#define spn_EGRESS_MCAST_EF_PRI  "egress_mcast_ef_pri"
#define spn_EGRESS_MCAST_NEF_PRI  "egress_mcast_nef_pri"
/*
 * Defines the QE2000 "len_adj" location in Route header
 *    0: Word 2, Bits  7-10
 *    1: Word 2, bits 12-15
 */
#define spn_PACKET_ADJUST_FORMAT  "packet_adjust_format"
/*
 * Valid on QE2000 only: Egress mcast descriptor size properties for EF and non-EF
 * the size is 2^n so, if set to 5, the size is 32 entries
 * the maximum size is 64 or n=6  minimum size is n=3
 * 
 * can be set for all units
 * egress_mcast_ef_desc=5
 * 
 * can be set for a particular unit (4)
 * egress_mcast_ef_desc.4=5
 * 
 * can be set for a particular port (2) on a particular unit (4)
 * egress_mcast_ef_desc.port2.4=5
 * 
 * if this property is not set the descriptors are distributed equally
 * based on the total number of SPI subports used - derived from qe_spi_0
 * and qe_spi_1
 */
#define spn_EGRESS_MCAST_EF_DESC_SZ  "egress_mcast_ef_desc_sz"
#define spn_EGRESS_MCAST_NEF_DESC_SZ  "egress_mcast_nef_desc_sz"

/* scheduling template for local queues */
#define spn_TM_LOCAL_SCHED_DISCIPLINE_TEMPLATE  "tm_local_sched_discipline_template"

/* scheduling template for nodes higher up in hierarchy */
#define spn_TM_SCHED_DISCIPLINE_TEMPLATE  "tm_sched_discipline_template"
/*
 * Following properties are valid on BME or SE or LCM or BME+SE device
 *     spn_BM_DEVICE_MODE
 *        - specifies mode the BM device is running with
 *          0: BME only
 *          1: SE only
 *          2: BME+SE
 *          3: LCM only
 */
#define spn_BM_DEVICE_MODE  "bm_device_mode"
/*
 * Following properties are vaild on BME
 *     spn_BME_SWITCH_CONTROLLER_ID
 *   - switch controller id for the BME
 *     spn_BME_NUM_ESETS
 *        - Number of ESETS. Relevant for Polaris/QE2000 configuration.
 *          This configuration allows 1024 ESETS. ESETS above 128 require
 *          special VOQ allocation algorithm.
 */
#define spn_BME_SWITCH_CONTROLLER_ID  "bme_switch_controller_id"
#define spn_BME_NUM_ESETS  "bme_num_esets"
#define spn_ENABLE_ALL_MODULE_ARBITRATION  "enable_all_module_arbitration"
/*
 * 64 => arbitration port algorithm reserves odd buckets for nef
 *       (optimized for Nodes)
 * 32 => arbitration port algorithm reserves odd entries from same bucket
 *       for nef (optimized for ports)
 */
#define spn_ARBITRATION_PORT_MAX_NODES  "arbitration_port_max_nodes"
#define spn_SBX_MC_QID_BASE  "sbx_mc_qid_base"

/* Following properties are valid on sirius */

/* Define number of external ram (ddr) devices used */
#define spn_EXT_RAM_PRESENT  "ext_ram_present"

/* Define number of columns of external ram (ddr) devices used */
#define spn_EXT_RAM_COLUMNS  "ext_ram_columns"

/* Define number of rows of external ram (ddr) devices used */
#define spn_EXT_RAM_ROWS  "ext_ram_rows"

/* Define number of banks of external ram (ddr) devices used */
#define spn_EXT_RAM_BANKS  "ext_ram_banks"
#define spn_SIRIUS_DDR_HW_TRAIN  "sirius_ddr_hw_train"
#define spn_SIRIUS_DDR_SW_DDR_TRAIN_INTERVAL  "sirius_ddr_sw_ddr_train_interval"
#define spn_SIRIUS_SW_DDR_TRAIN_THREAD_PRI  "sirius_sw_ddr_train_thread_pri"
#define spn_SIRIUS_DDR3_CLOCK_MHZ  "sirius_ddr3_clock_mhz"
#define spn_SIRIUS_DDR3_MEM_GRADE  "sirius_ddr3_mem_grade"
#define spn_SIRIUS_DDR3_DQ_ADJUST  "sirius_ddr3_dq_adjust"
#define spn_SIRIUS_DDR3_CTL_ADJUST  "sirius_ddr3_ctl_adjust"
#define spn_SIRIUS_DDR3_RD_EN_ADJUST  "sirius_ddr3_rd_en_adjust"
#define spn_SIRIUS_DDR3_TREAD_ENB  "sirius_ddr3_tread_enb"
#define spn_SIRIUS_DDR3_READ_DLY  "sirius_ddr3_read_dly"
#define spn_SIRIUS_DDR3_READ_EN_VDL  "sirius_ddr3_read_en_vdl"
#define spn_SIRIUS_DDR3_READ_VDL  "sirius_ddr3_read_vdl"
/*
 * Following properties are vaild on LCM
 *     spn_LCM_PASSTHROUGH_MODE
 *        - 1 for passthrough mode, 0 for 1+1 mode
 *     spn_LCM_ACTIVE_PLANE_ID
 *        - 0/1 specify active data plane id
 *     spn_LCM_DATAPLANE_0_MAP
 *       - per port(link) property, specify the destination port(link) for the port on
 *          dataplane 0
 *     spn_LCM_DATAPLANE_1_MAP
 *        - per port(link) property, specify the destination port(link) for the port on
 *          dataplane 1
 *     spn_LCM_XCFG_AB_INPUT_POLARITY_REVERSED
 */
#define spn_LCM_PASSTHROUGH_MODE  "lcm_passthrough_mode"
#define spn_LCM_DATAPLANE_0_MAP  "lcm_dataplane_0_map"
#define spn_LCM_DATAPLANE_1_MAP  "lcm_dataplane_1_map"
#define spn_LCM_XCFG_AB_INPUT_POLARITY_REVERSED  "lcm_xcfg_ab_input_polarity_reversed"
/*
 * Following properties are used by the diag shell only
 *     spn_DIAG_CHASSIS
 *        - defines the chassis type, 0 standalone
 *          1 fabric card + line cards
 *     spn_DIAG_COSQ_INIT
 *        - diag shell performs gport adds. Must be used with bcm_cosq_init=0
 */
#define spn_DIAG_CHASSIS  "diag_chassis"
#define spn_DIAG_SERDES_MASK  "diag_serdes_mask"
#define spn_DIAG_NODES_MASK  "diag_nodes_mask"
#define spn_DIAG_SLAVE_FC  "diag_slave_fc"
#define spn_DIAG_SLOT  "diag_slot"
#define spn_DIAG_COSQ_INIT  "diag_cosq_init"
#define spn_DIAG_EASY_RELOAD  "diag_easy_reload"
#define spn_DIAG_DISABLE_INTERRUPTS  "diag_disable_interrupts"
/*
 *  Specifies to enable or disable MACSEC feature on the 
 *  specified port. MACSEC feature might be provided by a PHY device attached to 
 *  switch port. (Default is to disable MACSEC)
 * 
 */
#define spn_MACSEC_ENABLE  "macsec_enable"

/*  specifies the MDIO address for the MACSEC PHY device. */
#define spn_MACSEC_DEV_ADDR  "macsec_dev_addr"

/*  specifies Port index within the multi-port MACSEC PHY device. */
#define spn_MACSEC_PORT_INDEX  "macsec_port_index"

/* Tab width for diagnostics (especially 'show counters') */
#define spn_DIAG_TABS  "diag_tabs"
/*
 * ASCII comma character for show counters
 * Use 44 for comma, 46 for period, 0 for none
 */
#define spn_DIAG_COMMA  "diag_comma"
#define spn_SRP_ACK_AGING_ON  "SRP_ACK_AGING_ON"
#define spn_EAV_SRP_INTERVAL  "EAV_SRP_INTERVAL"
#define spn_EAV_DISCOVERY_SRC_MAC  "EAV_DISCOVERY_SRC_MAC"
#define spn_EAV_TIMESYNC_MONITOR_PBMP  "EAV_TIMESYNC_MONITOR_PBMP"
#define spn_EAV_DISCOVERY_MASTER  "EAV_DISCOVERY_MASTER"
#define spn_EAV_TIMESYNC_INTERVAL  "EAV_TIMESYNC_INTERVAL"
#define spn_EAV_TIMESYNC_SPECIAL_LOOP_PBMP  "EAV_TIMESYNC_SPECIAL_LOOP_PBMP"
#define spn_EAV_TIMESYNC_DISABLE_PDELAY  "EAV_TIMESYNC_DISABLE_PDELAY"
#define spn_DIAG_EMULATOR_PARTIAL_INIT  "diag_emulator_partial_init"
/*
 * PCI device ID override allows you to pretend you are running
 * on a different chip (e.g. force 56504 driver to run on 56514)
 * NOTE: this one is actually in sysconf.c, not the driver.
 */
#define spn_PCI_OVERRIDE_DEV  "pci_override_dev"
/*
 * PCI revision ID override allows you to pretend you are running
 * on a different revision of a chip (e.g. force 56504 A0 driver to run on 56504 B0)
 * NOTE: this one is actually in sysconf.c, not the driver.
 */
#define spn_PCI_OVERRIDE_REV  "pci_override_rev"
#define spn_DIAG_ASSIGN_SYSPORT  "diag_assign_sysport"
#define spn_DEFIP_CAM_TM  "defip_cam_tm"
#define spn_FP_CAM_TM  "fp_cam_tm"
#define spn_VFP_CAM_TM  "vfp_cam_tm"
#define spn_EFP_CAM_TM  "efp_cam_tm"
#define spn_EMULATION_REGS  "emulation_regs"
#define spn_OTP_MEM_REPAIR_REG  "otp_mem_repair_reg"
#define spn_OTP_MEM_REPAIR_VAL  "otp_mem_repair_val"
#define spn_FIFO_DELAY_VALUE  "fifo_delay_value"
#define spn_BCM56840_CONFIG  "bcm56840_config"
#define spn_TCAM_DAC_VALUE  "tcam_dac_value"
#define spn_TCAM_PTR_DIST  "tcam_ptr_dist"
#define spn_EXT_TCAM_USE_MIDL  "ext_tcam_use_midl"

/* Enable hardware cable diagnostic function on 546x PHY devices */
#define spn_CABLE_DIAG_HW  "cable_diag_hw"
#define spn_LRP_BYPASS  "lrp_bypass"
#define spn_SPI_LOOPBACK  "spi_loopback"
#define spn_BCM88025_HPP_FREQ  "bcm88025_hpp_freq"
#define spn_BCM88025_SWS_FREQ  "bcm88025_sws_freq"
#define spn_BCM88025_UCODE  "bcm88025_ucode"
#define spn_BCM88025_DDR_TYPE  "bcm88025_ddr_type"
#define spn_BCM88025_SPI_FREQ  "bcm88025_spi_freq"
#define spn_DDR_TRAIN_NUM_ADDRS  "ddr_train_num_addrs"
#define spn_SEED  "seed"
#define spn_WIDE_SRAM0_X18  "wide_sram0_x18"
#define spn_NP0_ADDR_WIDTH  "np0_addr_width"
#define spn_NP0_DATA_WIDTH  "np0_data_width"
#define spn_NP1_ADDR_WIDTH  "np1_addr_width"
#define spn_NP1_DATA_WIDTH  "np1_data_width"
#define spn_WP_ADDR_WIDTH  "wp_addr_width"
#define spn_WP_DATA_WIDTH  "wp_data_width"
#define spn_WIDE_SRAM1_X18  "wide_sram1_x18"
/*
 * Valid only on BCM 88025 chip.
 * This configuration enables IPv6 feature.
 * Requires microcode that supports IPv6
 * Cannot coexist with Mac-in-Mac feature
 */
#define spn_IPV6_ENABLE  "ipv6_enable"
/*
 * Valid only on BCM 88025 chip.
 * This configuration enables Mac-in-Mac feature.
 * Requires microcode that supports MiM.
 * Cannot coexist with IPv6 feature.
 */
#define spn_MIM_ENABLE  "mim_enable"
/*
 * Valid only on BCM 88025 chip.
 * This configuration controls size of host memory allocated for LPM operations
 */
#define spn_L3_LPM_HOST_SRAM_FACTOR  "l3_lpm_host_sram_factor"
/*
 * Valid only on BCM 88025 chip.
 * This configuration sets the size of Level2 IPv4 Destination Address LPM table.
 * If not set, system determines size to allocate based on free memory remaining.
 */
#define spn_L3_V4UC_DA_DEV_MEMSIZE  "l3_v4uc_da_dev_memsize"
/*
 * Valid only on BCM 88025 chip.
 * This configuration sets the size of Level2 IPv4 Source Address LPM table.
 * If set, must be less than size of Ipv4 DA LPM table.
 * If not set, system allocates 250f size configured for IPv4 DA LPM Table.
 * If set to 0, allocates 0 memory for SA Table.
 */
#define spn_L3_V4UC_SA_DEV_MEMSIZE  "l3_v4uc_sa_dev_memsize"
/*
 * Valid only on BCM 88025 chip.
 * This configuration sets the size of Level2 IPv6 Destination Address LPM table.
 * If not set, system determines size to allocate based on free memory remaining.
 */
#define spn_L3_V6UC_DA_DEV_MEMSIZE  "l3_v6uc_da_dev_memsize"
/*
 * Valid only on BCM 88025 chip.
 * This configuration sets the size of Level2 IPv6 Source Address LPM table.
 * If set, must be less than size of Ipv6 DA LPM table.
 * If not set, system allocates 250f size configured for IPv6 DA LPM Table.
 * If set to 0, allocates 0 memory for SA Table.
 */
#define spn_L3_V6UC_SA_DEV_MEMSIZE  "l3_v6uc_sa_dev_memsize"
/*
 * Valid only on BCM 88025 chip.
 * This configuration sets the size of Level2 MAC Lookup Table.
 * If not set, system determines size to allocate based on free memory remaining.
 */
#define spn_MAC_DEV_MEMSIZE  "mac_dev_memsize"

/* Number of widest externel TCAM (ESM) data entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_ESM_ENTRIES  "ism_config_esm_entries"

/* Number of widest vlan xlate entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_XLATE_ENTRIES  "ism_config_xlate_entries"

/* Number of widest l2 entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_L2_ENTRIES  "ism_config_l2_entries"

/* Number of widest l3 entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_L3_ENTRIES  "ism_config_l3_entries"

/* Number of widest egress vlan xlate entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_EGR_XLATE_ENTRIES  "ism_config_egr_xlate_entries"

/* Number of widest mpls entries in terms of 1k quanta. */
#define spn_ISM_CONFIG_MPLS_ENTRIES  "ism_config_mpls_entries"
/*
 * Valid on BCM 88020 and 88025 chips.
 * This switch turns on and off OAM reception by enabling or disabling
 * the PPE rules that detect OAM packets.
 */
#define spn_OAM_RX_ENABLE  "oam_rx_enable"
/*
 * Valid on BCM 88020 and 88025 chips.
 * This switch turns on and off OAM transmission by enabling or disabling
 * the LRP Service Processor bubble generation.
 */
#define spn_OAM_TX_ENABLE  "oam_tx_enable"
/*
 * The oam_spi_lb_port and oam_spi_lb_queue soc properties allow for run-time
 * configuration of the loopback SPI port used by OAM for up MEPs.  This only
 * needs to be specified if the default port configuration in fe2000.c is
 * over-ridden with port assignments in the config.bcm.
 */
#define spn_OAM_SPI_LB_PORT  "oam_spi_lb_port"
/*
 * The oam_spi_lb_port and oam_spi_lb_queue soc properties allow for run-time
 * configuration of the loopback SPI port used by OAM for up MEPs.  This queue
 * number can be determined by running bcm.user with the oam_spi_lb_port
 * specified and using g2util swsdump to print out all the queue numbers.
 * Then update the config specifying the first (of two) QID associated with
 * the SPI loopback port.
 */
#define spn_OAM_SPI_LB_QUEUE  "oam_spi_lb_queue"
#define spn_V4MC_STR_SEL  "v4mc_str_sel"
#define spn_V4UC_STR_SEL  "v4uc_str_sel"
#define spn_BCM88020_UCODE  "bcm88020_ucode"
#define spn_SMAC_PYLD_PERCENT  "smac_pyld_percent"
#define spn_DMAC_PYLD_PERCENT  "dmac_pyld_percent"
#define spn_IPV4_SA_PYLD_PERCENT  "ipv4_sa_pyld_percent"
#define spn_IPV4_DA_PYLD_PERCENT  "ipv4_da_pyld_percent"
#define spn_IPV4MC_SG_PYLD_PERCENT  "ipv4mc_sg_pyld_percent"
#define spn_IPV4MC_G_PYLD_PERCENT  "ipv4mc_g_pyld_percent"
#define spn_IPV6_SA_PYLD_PERCENT  "ipv6_sa_pyld_percent"
#define spn_IPV6_SA_LPM_PYLD_PERCENT  "ipv6_sa_lpm_pyld_percent"
#define spn_IPV6_DA_PYLD_PERCENT  "ipv6_da_pyld_percent"
#define spn_IPV6_DA_LPM_PYLD_PERCENT  "ipv6_da_lpm_pyld_percent"
#define spn_IPV6_MC_PYLD_PERCENT  "ipv6_mc_pyld_percent"
#define spn_IPV6_MC_EM_PERCENT  "ipv6_mc_em_percent"
#define spn_INGR_COUNTER_PERCENT  "ingr_counter_percent"
#define spn_EGR_COUNTER_PERCENT  "egr_counter_percent"
#define spn_EXC_COUNTER_PERCENT  "exc_counter_percent"
#define spn_FTE_PERCENT  "fte_percent"
#define spn_ETE_PERCENT  "ete_percent"
#define spn_FTE_PREALLOTMENT  "fte_preallotment"
#define spn_ETE_PREALLOTMENT  "ete_preallotment"
#define spn_IGMP_PROXY_MODE  "igmp_proxy_mode"
#define spn_POLICER_BASE_RATE  "policer_base_rate"
/*
 * Valid only on BCM 88025 Chips.
 * Config sets the size of IPv6 Destination Address Exact Match table
 */
#define spn_BCM88025_V6_DHOSTS  "bcm88025_v6_dhosts"
/*
 * Valid only on BCM 88025 Chips.
 * Config sets the size of IPv6 Source Address Exact Match table
 */
#define spn_BCM88025_V6_SHOSTS  "bcm88025_v6_shosts"
#define spn_DIAG_HG_AS_GE  "diag_hg_as_ge"
#define spn_DIAG_HG_AS_XE  "diag_hg_as_xe"
/*
 * ThunderBolt flow id size for user config
 * flow id > tb_flow_id_size will be reserved
 * for internal use
 */
#define spn_TB_FLOW_ID_SIZE  "tb_flow_id_size"

/* Board driver name */
#define spn_BOARD_NAME  "board_name"

/* Board driver start flags */
#define spn_BOARD_FLAGS  "board_flags"

/* WAN ports select */
#define spn_PBMP_WAN_PORT  "pbmp_wan_port"

/* Dual IMP ports enable */
#define spn_DUAL_IMP_ENABLE  "dual_imp_enable"

/* Auto enable MAC Low Power mode */
#define spn_AUTO_ENABLE_MAC_LOW_POWER  "auto_enable_mac_low_power"

/* Configure port as standalone/egress only */
#define spn_8802X_EGRESS_ONLY  "8802x_egress_only"

/* Configure field processor for atomic updates */
#define spn_FIELD_ATOMIC_UPDATE  "field_atomic_update"

/* Define the bitmask for destination port data in the module/port info field */
#define spn_HIGIG_DESTPORT_MASK  "higig_destport_mask"

/* Configure mapping from fabric destination port in the module/port info field to destination ucode port */
#define spn_88025_HG_DESTPORT  "88025_hg_destport"

/* Specify the stable cache option for Warm Boot operations */
#define spn_STABLE_LOCATION  "stable_location"

/* Specify the stable cache flags to configure Warm Boot operations */
#define spn_STABLE_FLAGS  "stable_flags"

/* Specify the stable cache size in bytes used for Warm boot operations */
#define spn_STABLE_SIZE  "stable_size"
/*
 * If the stable cache location is BCM_SWITCH_STABLE_APPLICATION, the local
 * file system will be used to save the stable cache data with this filename
 */
#define spn_STABLE_FILENAME  "stable_filename"

/* NSE SYNC_IN divider */
#define spn_PHY_1588_TS_DIVIDER  "phy_1588_ts_divider"

/* IEEE1588 DPLL coeff. K1 */
#define spn_PHY_1588_DPLL_K1  "phy_1588_dpll_k1"

/* IEEE1588 DPLL coeff. K2 */
#define spn_PHY_1588_DPLL_K2  "phy_1588_dpll_k2"

/* IEEE1588 DPLL coeff. K3 */
#define spn_PHY_1588_DPLL_K3  "phy_1588_dpll_k3"

/* Initial phase values for the IEEE1588 DPLL, lower 32 bits */
#define spn_PHY_1588_DPLL_PHASE_INITIAL_LO  "phy_1588_dpll_phase_initial_lo"

/* Initial phase values for the IEEE1588 DPLL, upper 32 bits */
#define spn_PHY_1588_DPLL_PHASE_INITIAL_HI  "phy_1588_dpll_phase_initial_hi"

/* IEEE1588 DPLL mode, 0 - phase lock, 1 - frequency lock */
#define spn_PHY_1588_DPLL_FREQUENCY_LOCK  "phy_1588_dpll_frequency_lock"

/* Phy operating in the reverse direction */
#define spn_PORT_PHY_MODE_REVERSE  "port_phy_mode_reverse"
/*
 * Device Interconnect Mode (PCI-EB3/VLI).
 * Currently used for BCM88732
 * 0 = PCI, 1 = EB3/VLI
 */
#define spn_DEVICE_EB_VLI  "device_eb_vli"
/*
 * BCM88732(Shadow) Flow Control Mode
 * 0 = InBand(IB), 1 = OutofBand(OOB)
 * Default is OOB for Shadow         
 */
#define spn_BCM88732_USE_OOB  "bcm88732_use_oob"
/*
 * BCM88732(Shadow) Device Mode
 * 0 = XGS, 1 = PETRAB
 */
#define spn_BCM88732_DEVICE_MODE  "bcm88732_device_mode"
/*
 * Shadow Port Configuration
 * Front Panel ports:2X40G Switch Panel ports(Interlaken):2X40
 */
#define spn_BCM88732_2X40_2X40  "bcm88732_2x40_2x40"
/*
 * Shadow Port Configuration
 * Front Panel ports:2x40G Switch Panel ports(Interlaken):1x40G
 */
#define spn_BCM88732_2X40_1X40  "bcm88732_2x40_1x40"
/*
 * Shadow Port Configuration
 * Front Panel ports:8x10G Switch Panel ports(Interlaken):1x40G
 */
#define spn_BCM88732_8X10_1X40  "bcm88732_8x10_1x40"
/*
 * Shadow Port Configuration
 * Front Panel ports:8x10G Switch Panel ports(Interlaken):2x40G
 */
#define spn_BCM88732_8X10_2X40  "bcm88732_8x10_2x40"
/*
 * Shadow Port Configuration
 * Front Panel ports:1X40G(XLAUI) Switch Panel(XAUI) ports:4X10G
 */
#define spn_BCM88732_1X40_4X10  "bcm88732_1x40_4x10"
/*
 * Shadow Port Configuration
 * Front Panel ports:4x10G(XFI/SFI) Switch Panel ports(XAUI):4x10G
 */
#define spn_BCM88732_4X10_4X10  "bcm88732_4x10_4x10"
/*
 * Shadow Port Configuration
 * Front Panel ports:2x40G Switch Panel ports(Interlaken):2x40G
 */
#define spn_BCM88732_2X40_2X40E  "bcm88732_2x40_2x40E"
/*
 * Shadow Port Configuration
 * Front Panel ports:2x40G Switch Panel ports:8x12G
 */
#define spn_BCM88732_2X40_8X12  "bcm88732_2x40_8x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:8x10G Switch Panel ports:8x12G
 */
#define spn_BCM88732_8X10_8X12  "bcm88732_8x10_8x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:1x40G,4x10G Switch Panel ports:8x12G
 */
#define spn_BCM88732_1X40_4X10_8X12  "bcm88732_1x40_4x10_8x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:4x10G,1x40G Switch Panel ports:8x12G
 */
#define spn_BCM88732_4X10_1X40_8X12  "bcm88732_4x10_1x40_8x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:1x40G Switch Panel ports:4x12G
 */
#define spn_BCM88732_8X10_4X12  "bcm88732_8x10_4x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:8x10G Switch Panel ports:2x12G
 */
#define spn_BCM88732_8X10_2X12  "bcm88732_8x10_2x12"
/*
 * Shadow Port Configuration
 * Front Panel ports:6x10G Switch Panel ports:2x12G
 */
#define spn_BCM88732_6X10_2X12  "bcm88732_6x10_2x12"
/*
 * CMC in CMICm used by the microController
 * suffix with _pci _uc0 etc..
 */
#define spn_CMC  "cmc"

/* Enable Fast SCHAN present in CMICm */
#define spn_FSCHAN_ENABLE  "fschan_enable"
/*
 * On 5644x devices MMU, the ports can have its packet buffer either
 * the Interal memory or the External DRAM. Set the following pbmp to
 * configure specific ports for external memory.
 */
#define spn_PBMP_EXT_MEM  "pbmp_ext_mem"
/*
 *  Specifies to enable or disable FCMAP feature on the 
 *  specified port. FCMAP feature might be provided by a PHY device attached to 
 *  switch port. (Default is to disable FCMAP)
 * 
 */
#define spn_FCMAP_ENABLE  "fcmap_enable"

/*  specifies the MDIO address for the FCMAP PHY device. */
#define spn_FCMAP_DEV_ADDR  "fcmap_dev_addr"

/*  specifies Port index within the multi-port FCMAP PHY device. */
#define spn_FCMAP_PORT_INDEX  "fcmap_port_index"

/* MMU config tool prefix */
#define spn_BUF  "buf"

/* MMU config tool prefix */
#define spn_MAP  "map"

/* MMU config tool object name */
#define spn_PRI  "pri"

/* MMU config tool object name */
#define spn_DEVICE  "device"

/* MMU config tool object name */
#define spn_POOL  "pool"

/* MMU config tool object name */
#define spn_PORT  "port"

/* MMU config tool object name */
#define spn_PRIGROUP  "prigroup"

/* MMU config tool object name */
#define spn_QUEUE  "queue"

/* MMU config tool object name */
#define spn_MQUEUE  "mqueue"

/* MMU config tool object name */
#define spn_EQUEUE  "equeue"

/* MMU config tool attribute name */
#define spn_SIZE  "size"

/* MMU config tool attribute name */
#define spn_YELLOW_SIZE  "yellow_size"

/* MMU config tool attribute name */
#define spn_RED_SIZE  "red_size"

/* MMU config tool attribute name */
#define spn_GUARANTEE  "guarantee"

/* MMU config tool attribute name */
#define spn_HEADROOM  "headroom"

/* MMU config tool attribute name */
#define spn_USER_DELAY  "user_delay"

/* MMU config tool attribute name */
#define spn_SWITCH_DELAY  "switch_delay"

/* MMU config tool attribute name */
#define spn_POOL_SCALE  "pool_scale"

/* MMU config tool attribute name */
#define spn_POOL_LIMIT  "pool_limit"

/* MMU config tool attribute name */
#define spn_POOL_RESUME  "pool_resume"

/* MMU config tool attribute name */
#define spn_POOL_FLOOR  "pool_floor"

/* MMU config tool attribute name */
#define spn_YELLOW_LIMIT  "yellow_limit"

/* MMU config tool attribute name */
#define spn_YELLOW_RESUME  "yellow_resume"

/* MMU config tool attribute name */
#define spn_RED_LIMIT  "red_limit"

/* MMU config tool attribute name */
#define spn_RED_RESUME  "red_resume"

/* MMU config tool attribute name */
#define spn_DEVICE_HEADROOM_ENABLE  "device_headroom_enable"

/* MMU config tool attribute name */
#define spn_PORT_GUARANTEE_ENABLE  "port_guarantee_enable"

/* MMU config tool attribute name */
#define spn_PORT_MAX_ENABLE  "port_max_enable"

/* MMU config tool attribute name */
#define spn_FLOW_CONTROL_ENABLE  "flow_control_enable"

/* MMU config tool attribute name */
#define spn_DISCARD_ENABLE  "discard_enable"

/* MMU config tool attribute name */
#define spn_COLOR_DISCARD_ENABLE  "color_discard_enable"

/* MMU config tool attribute name */
#define spn_PKT_SIZE  "pkt_size"

/* UC0 Messaging control */
#define spn_UC_MSG_CTRL_0  "uc_msg_ctrl_0"

/* UC1 Messaging control */
#define spn_UC_MSG_CTRL_1  "uc_msg_ctrl_1"

/* UC Messaging thread priority */
#define spn_UC_MSG_THREAD_PRI  "uc_msg_thread_pri"

/* UC Messaging ctl mutex timeout in microsecs */
#define spn_UC_MSG_CTL_TIMEOUT  "uc_msg_ctl_timeout"

/* UC Messaging send queue timeout in microsecs */
#define spn_UC_MSG_QUEUE_TIMEOUT  "uc_msg_queue_timeout"

/* UC Messaging send timeout in microsecs */
#define spn_UC_MSG_SEND_TIMEOUT  "uc_msg_send_timeout"

/* UC Messaging send retry delay in microseconds */
#define spn_UC_MSG_SEND_RETRY_DELAY  "uc_msg_send_retry_delay"

/* TX beacon messaging timeout in microsecs */
#define spn_UC_MSG_TX_BEACON_TIMEOUT  "uc_msg_tx_beacon_timeout"
/*
 * In 5644x, 48 queues will be shared across host cpu and
 * other micro controllers, this variable can be configured
 * suffix with _pci _uc0 etc..
 */
#define spn_NUM_QUEUES  "num_queues"

/* Valid Micro controllers bit map */
#define spn_UC_VALID_BMP  "uc_valid_bmp"

/* MMU configuration of maximum number of queues */
#define spn_MMU_MAX_QUEUES  "mmu_max_queues"

/* MMU configuration of maximum number of aggregate nodes */
#define spn_MMU_MAX_NODES  "mmu_max_nodes"

/* COS levels per subscriber */
#define spn_MMU_SUBSCRIBER_NUM_COS_LEVEL  "mmu_subscriber_num_cos_level"

/* Enable Extended Queues */
#define spn_MMU_EXT_QUEUES_ENABLED  "mmu_ext_queues_enabled"

/* MMU configuration of maximum number of classic queues */
#define spn_MMU_MAX_CLASSIC_QUEUES  "mmu_max_classic_queues"

/* BFD COS queue */
#define spn_BFD_COSQ  "bfd_cosq"

/* Memory allocated for BFD encapsulation data (in bytes) */
#define spn_BFD_ENCAP_MEMORY_SIZE  "bfd_encap_memory_size"

/* Number of BFD simple password authentication keys */
#define spn_BFD_SIMPLE_PASSWORD_KEYS  "bfd_simple_password_keys"

/* Number of BFD SHA1 authentication keys */
#define spn_BFD_SHA1_KEYS  "bfd_sha1_keys"

/* Number of BFD sessions */
#define spn_BFD_NUM_SESSIONS  "bfd_num_sessions"

/* PTP frequency synthesizer DFPLL value for state 1 and k1 filter parameter */
#define spn_PTP_SYNTH_1_K1  "ptp_synth_1_k1"

/* PTP frequency synthesizer DFPLL value for state 1 and k1k2 filter parameter */
#define spn_PTP_SYNTH_1_K1K2  "ptp_synth_1_k1k2"

/* PTP frequency synthesizer DFPLL value for state 1 and k1k3 filter parameter */
#define spn_PTP_SYNTH_1_K1K3  "ptp_synth_1_k1k3"

/* PTP frequency synthesizer DFPLL value for state 1 and k4 filter parameter */
#define spn_PTP_SYNTH_1_K4  "ptp_synth_1_k4"

/* PTP frequency synthesizer DFPLL value for state 1 and valid_thresh parameter */
#define spn_PTP_SYNTH_1_VALID_THRESH  "ptp_synth_1_valid_thresh"

/* PTP frequency synthesizer DFPLL value for state 1 and invalid_thresh parameter */
#define spn_PTP_SYNTH_1_INVALID_THRESH  "ptp_synth_1_invalid_thresh"

/* PTP frequency synthesizer DFPLL value for state 2 and k1 filter parameter */
#define spn_PTP_SYNTH_2_K1  "ptp_synth_2_k1"

/* PTP frequency synthesizer DFPLL value for state 2 and k1k2 filter parameter */
#define spn_PTP_SYNTH_2_K1K2  "ptp_synth_2_k1k2"

/* PTP frequency synthesizer DFPLL value for state 2 and k1k3 filter parameter */
#define spn_PTP_SYNTH_2_K1K3  "ptp_synth_2_k1k3"

/* PTP frequency synthesizer DFPLL value for state 2 and k4 filter parameter */
#define spn_PTP_SYNTH_2_K4  "ptp_synth_2_k4"

/* PTP frequency synthesizer DFPLL value for state 2 and valid_thresh parameter */
#define spn_PTP_SYNTH_2_VALID_THRESH  "ptp_synth_2_valid_thresh"

/* PTP frequency synthesizer DFPLL value for for state 2 and invalid_thresh parameter */
#define spn_PTP_SYNTH_2_INVALID_THRESH  "ptp_synth_2_invalid_thresh"

/* PTP frequency synthesizer DFPLL value for valid_input parameter */
#define spn_PTP_SYNTH_VALID_INPUT_THRESH  "ptp_synth_valid_input_thresh"

/* PTP frequency synthesizer DFPLL value for nominal_period parameter */
#define spn_PTP_SYNTH_NOMINAL_PERIOD  "ptp_synth_nominal_period"

/* PTP backplane DFPLL value for state 1 and k1 filter parameter */
#define spn_PTP_BACKPLANE_1_K1  "ptp_backplane_1_k1"

/* PTP backplane DFPLL value for state 1 and k1k2 filter parameter */
#define spn_PTP_BACKPLANE_1_K1K2  "ptp_backplane_1_k1k2"

/* PTP backplane DFPLL value for state 1 and k1k3 filter parameter */
#define spn_PTP_BACKPLANE_1_K1K3  "ptp_backplane_1_k1k3"

/* PTP backplane DFPLL value for state 1 and k4 filter parameter */
#define spn_PTP_BACKPLANE_1_K4  "ptp_backplane_1_k4"

/* PTP backplane DFPLL value for state 1 and valid_thresh parameter */
#define spn_PTP_BACKPLANE_1_VALID_THRESH  "ptp_backplane_1_valid_thresh"

/* PTP backplane DFPLL value for state 1 and invalid_thresh parameter */
#define spn_PTP_BACKPLANE_1_INVALID_THRESH  "ptp_backplane_1_invalid_thresh"

/* PTP backplane DFPLL value for state 2 and k1 filter parameter */
#define spn_PTP_BACKPLANE_2_K1  "ptp_backplane_2_k1"

/* PTP backplane DFPLL value for state 2 and k1k2 filter parameter */
#define spn_PTP_BACKPLANE_2_K1K2  "ptp_backplane_2_k1k2"

/* PTP backplane DFPLL value for state 2 and k1k3 filter parameter */
#define spn_PTP_BACKPLANE_2_K1K3  "ptp_backplane_2_k1k3"

/* PTP backplane DFPLL value for state 2 and k4 filter parameter */
#define spn_PTP_BACKPLANE_2_K4  "ptp_backplane_2_k4"

/* PTP backplane DFPLL value for state 2 and valid_thresh parameter */
#define spn_PTP_BACKPLANE_2_VALID_THRESH  "ptp_backplane_2_valid_thresh"

/* PTP backplane DFPLL value for state 2 and invalid_thresh parameter */
#define spn_PTP_BACKPLANE_2_INVALID_THRESH  "ptp_backplane_2_invalid_thresh"

/* PTP backplane DFPLL value for valid_input parameter */
#define spn_PTP_BACKPLANE_VALID_INPUT_THRESH  "ptp_backplane_valid_input_thresh"

/* PTP backplane DFPLL value for nominal_period parameter */
#define spn_PTP_BACKPLANE_NOMINAL_PERIOD  "ptp_backplane_nominal_period"

/* PTP Timestamping PLL value for fref parameter */
#define spn_PTP_TS_PLL_FREF  "ptp_ts_pll_fref"

/* PTP Timestamping PLL value for pdiv parameter */
#define spn_PTP_TS_PLL_PDIV  "ptp_ts_pll_pdiv"

/* PTP Timestamping PLL value for n parameter */
#define spn_PTP_TS_PLL_N  "ptp_ts_pll_n"

/* pPTP Timestamping PLL value for mndiv parameter */
#define spn_PTP_TS_PLL_MNDIV  "ptp_ts_pll_mndiv"

/* PTP Timestamping PLL value for ka parameter */
#define spn_PTP_TS_KA  "ptp_ts_ka"

/* PTP Timestamping PLL value for k1 parameter */
#define spn_PTP_TS_KI  "ptp_ts_ki"

/* PTP Timestamping PLL value for kp parameter */
#define spn_PTP_TS_KP  "ptp_ts_kp"

/* PTP Timestamping PLL value for vco_div2 parameter */
#define spn_PTP_TS_VCO_DIV2  "ptp_ts_vco_div2"

/* PTP BroadSync/10Mhz PLL value for fref parameter */
#define spn_PTP_BS_FREF  "ptp_bs_fref"

/* PTP BroadSync/10Mhz PLL value for pdiv parameter */
#define spn_PTP_BS_PDIV  "ptp_bs_pdiv"

/* PTP BroadSync/10Mhz PLL value for ndiv parameter */
#define spn_PTP_BS_NDIV_INT  "ptp_bs_ndiv_int"

/* PTP BroadSync/10Mhz PLL value for ndiv_frac parameter */
#define spn_PTP_BS_NDIV_FRAC  "ptp_bs_ndiv_frac"

/* PTP BroadSync/10Mhz PLL value for mndiv parameter */
#define spn_PTP_BS_MNDIV  "ptp_bs_mndiv"

/* PTP BroadSync/10Mhz PLL value for ka parameter */
#define spn_PTP_BS_KA  "ptp_bs_ka"

/* PTP BroadSync/10Mhz PLL value for k1 parameter */
#define spn_PTP_BS_KI  "ptp_bs_ki"

/* PTP BroadSync/10Mhz PLL value for kp parameter */
#define spn_PTP_BS_KP  "ptp_bs_kp"

/* PTP BroadSync/10Mhz PLL value for clk_dur_high parameter */
#define spn_PTP_BS_CLK_DUR_HIGH  "ptp_bs_clk_dur_high"

/* PTP BroadSync/10Mhz PLL value for clk_dur_low parameter */
#define spn_PTP_BS_CLK_DUR_LOW  "ptp_bs_clk_dur_low"

/* PTP BroadSync/10Mhz PLL value for hb_dur_high parameter */
#define spn_PTP_BS_HB_DUR_HIGH  "ptp_bs_hb_dur_high"

/* PTP BroadSync/10Mhz PLL value for hb_dur_low parameter */
#define spn_PTP_BS_HB_DUR_LOW  "ptp_bs_hb_dur_low"

/* PTP BroadSync/10Mhz PLL value for vco_div2 parameter */
#define spn_PTP_BS_VCO_DIV2  "ptp_bs_vco_div2"

/* PTP servo oscillator type */
#define spn_PTP_SERVO_OSC_TYPE  "ptp_servo_osc_type"

/* PTP servo transport type */
#define spn_PTP_SERVO_TRANSPORT_TYPE  "ptp_servo_transport_type"

/* PTP servo phase mode */
#define spn_PTP_SERVO_PHASE_MODE  "ptp_servo_phase_mode"

/* PTP servo bridge time */
#define spn_PTP_SERVO_BRIDGE_TIME  "ptp_servo_bridge_time"

/* Register Warm Boot event handler callback routine */
#define spn_WARMBOOT_EVENT_HANDLER_ENABLE  "warmboot_event_handler_enable"

/* Selects the TDM protocol to be used on all of the CES TDM ports. Valid protocols are either T1 or E1, the default is T1. */
#define spn_CES_PORT_TDM_PROTO  "ces_port_tdm_proto"

/* Sets the MAC address of the CES MII. If this is not specified then a default MAC of 00:F1:F2:F3:F4:F5 is used. */
#define spn_CES_MII_MAC  "ces_mii_mac"

/* Sets the CES MII port number. Default value is 0 */
#define spn_CES_MII_PORT_NUMBER  "ces_mii_port_number"

/* Sets the CES IPv4 address. Default value is 0 */
#define spn_CES_IPV4_ADDRESS  "ces_ipv4_address"

/* Sets the CES IPv6 address. Default value is 0 */
#define spn_CES_IPV6_ADDRESS  "ces_ipv6_address"
/*
 * For EA SDK only: describe EA unit X connected to Switch unit Y and its port Z.
 * 
 * ea_attach.portZ.Y=X 
 * 
 * For single EA unit attaches to switch unit 0, port25,
 * ea_attach.port25.0=0
 * 
 * For multiple EA units,
 * ea_attach.port25.0=0
 * ea_attach.port26.0=1
 * 
 * For EA unit that does not attach to switch,
 * ea_attach.port0.-1=0
 */
#define spn_EA_ATTACH  "ea_attach"

/* Memory Grade writte in Hex Value. eg. 10-10-10 grade = 0x101010 */
#define spn_DDR3_MEM_GRADE  "ddr3_mem_grade"

/* Memory Speed in MHz */
#define spn_DDR3_CLOCK_MHZ  "ddr3_clock_mhz"

/* Autorun Shmoo Tuning on Init */
#define spn_DDR3_AUTO_TUNE  "ddr3_auto_tune"
/*
 * Following properties are used to store DDR3 Auto Tuning Values.
 * Restores these values only if Auto-Tune is Off
 */
#define spn_DDR3_TUNE_RD_EN  "ddr3_tune_rd_en"
#define spn_DDR3_TUNE_WL0_RD_DQS_B0_0_3  "ddr3_tune_wl0_rd_dqs_b0_0_3"
#define spn_DDR3_TUNE_WL0_RD_DQS_B0_4_7  "ddr3_tune_wl0_rd_dqs_b0_4_7"
#define spn_DDR3_TUNE_WL0_RD_DQS_B1_0_3  "ddr3_tune_wl0_rd_dqs_b1_0_3"
#define spn_DDR3_TUNE_WL0_RD_DQS_B1_4_7  "ddr3_tune_wl0_rd_dqs_b1_4_7"
#define spn_DDR3_TUNE_WL1_RD_DQS_B0_0_3  "ddr3_tune_wl1_rd_dqs_b0_0_3"
#define spn_DDR3_TUNE_WL1_RD_DQS_B0_4_7  "ddr3_tune_wl1_rd_dqs_b0_4_7"
#define spn_DDR3_TUNE_WL1_RD_DQS_B1_0_3  "ddr3_tune_wl1_rd_dqs_b1_0_3"
#define spn_DDR3_TUNE_WL1_RD_DQS_B1_4_7  "ddr3_tune_wl1_rd_dqs_b1_4_7"
#define spn_DDR3_TUNE_WL0_WR_DQ_B0_0_3  "ddr3_tune_wl0_wr_dq_b0_0_3"
#define spn_DDR3_TUNE_WL0_WR_DQ_B0_4_7  "ddr3_tune_wl0_wr_dq_b0_4_7"
#define spn_DDR3_TUNE_WL0_WR_DQ_B1_0_3  "ddr3_tune_wl0_wr_dq_b1_0_3"
#define spn_DDR3_TUNE_WL0_WR_DQ_B1_4_7  "ddr3_tune_wl0_wr_dq_b1_4_7"
#define spn_DDR3_TUNE_WL1_WR_DQ_B0_0_3  "ddr3_tune_wl1_wr_dq_b0_0_3"
#define spn_DDR3_TUNE_WL1_WR_DQ_B0_4_7  "ddr3_tune_wl1_wr_dq_b0_4_7"
#define spn_DDR3_TUNE_WL1_WR_DQ_B1_0_3  "ddr3_tune_wl1_wr_dq_b1_0_3"
#define spn_DDR3_TUNE_WL1_WR_DQ_B1_4_7  "ddr3_tune_wl1_wr_dq_b1_4_7"
#define spn_DDR3_TUNE_ADDRC  "ddr3_tune_addrc"

/* Following properties are for DDR3 Tuning Overrides */
#define spn_DDR3_TREAD_ENB  "ddr3_tread_enb"
#define spn_DDR3_BANK_UNAVAIL_RD  "ddr3_bank_unavail_rd"
#define spn_DDR3_BANK_UNAVAIL_WR  "ddr3_bank_unavail_wr"
#define spn_DDR3_TRP_READ  "ddr3_trp_read"
#define spn_DDR3_TRP_WRITE  "ddr3_trp_write"
#define spn_DDR3_ROUND_ROBIN_READ  "ddr3_round_robin_read"
#define spn_DDR3_ROUND_ROBIN_WRITE  "ddr3_round_robin_write"

/* Enable Service Meter */
#define spn_GLOBAL_METER_CONTROL  "global_meter_control"
/*
 * Sets the MAC address of RCPU master. If this is not specified then a
 * default MAC of 00:aa:bb:22:33:00 is used. Note local CPU MAC address
 * is used in case of OOB RCPU master even this property is specified.
 */
#define spn_RCPU_SRC_MAC  "rcpu_src_mac"
/*
 * Sets the MAC address used by RCPU slave units. If this is not specified
 * then a default MAC of 00:00:11:22:33:00 is used. And the last octet is
 * replaced with unit number.
 */
#define spn_RCPU_LMAC  "rcpu_lmac"

/* This controls whether to extract the recovered clock or not. (same as SyncE) */
#define spn_PHY_CLOCK_ENABLE  "phy_clock_enable"
/*
 * Number of clock delay between the rising edge of MDC
 * and the starting data of MDIO
 */
#define spn_MDIO_OUTPUT_DELAY  "mdio_output_delay"

/* Enable VLAN queues */
#define spn_VLAN_QUEUE_ENABLE  "vlan_queue_enable"

/* Maximum levels for VLAN queues */
#define spn_VLAN_QUEUE_LEVELS_MAX  "vlan_queue_levels_max"


#endif /* __SOC_PROPERTY_H */
